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公开(公告)号：US20180173836A1
公开(公告)日：2018-06-21
申请号：US15896415
申请日：2018-02-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： TAEJOONG SONG , SANGHOON BAEK , SUNGWE CHO , JUNG-HO DO , GIYOUNG YANG , JINYOUNG LIM
IPC: G06F17/50 , H01L27/118 , H01L27/02
CPC classification number: G06F17/5077 , H01L27/0207 , H01L27/11807
Abstract: A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.
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公开(公告)号：US20170110372A1
公开(公告)日：2017-04-20
申请号：US15392725
申请日：2016-12-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： SANGHOON BAEK , JAE-HO PARK , SEOLUN YANG , TAEJOONG SONG , SANG-KYU OH
IPC: H01L21/8234 , H01L21/308 , H01L29/78 , H01L27/02 , H01L27/108 , H01L27/11 , H01L21/027 , H01L21/762
CPC classification number: H01L21/823431 , H01L21/0274 , H01L21/308 , H01L21/3086 , H01L21/76224 , H01L21/823437 , H01L21/823475 , H01L21/823481 , H01L27/0207 , H01L27/10879 , H01L27/10894 , H01L27/11 , H01L27/1104 , H01L27/1116 , H01L29/7851
Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.
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公开(公告)号：US20180174861A1
公开(公告)日：2018-06-21
申请号：US15899686
申请日：2018-02-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： JUNG-HO DO , JONGHOON JUNG , SANGHOON BAEK , SEUNGYOUNG LEE , TAEJOONG SONG , JINYOUNG LIM
IPC: H01L21/3213 , H01L21/8238
CPC classification number: H01L21/32139 , H01L21/823807 , H01L21/823821 , H01L21/823878
Abstract: A method of manufacturing a semiconductor device may include forming first trenches that define active patterns extending in a first direction on a substrate, forming first insulating layers filling the first trenches, forming first mask patterns extending in the first direction while having a first width along a second direction perpendicular to the first direction, forming a second mask pattern extending in the first direction while having a second width along the second direction, and forming a second trench that partly defines an active region by executing a first etching process that etches the active patterns and the first insulating layer using the first mask patterns and the second mask pattern.
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公开(公告)号：US20180019736A1
公开(公告)日：2018-01-18
申请号：US15649776
申请日：2017-07-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Ha-Young KIM , DALHEE LEE , Hyoung-Suk OH , Keunho LEE , TAEJOONG SONG , SUNGWE CHO
CPC classification number: H03K3/356104 , H03K3/35625 , H03K23/001
Abstract: A flip-flop includes an input interface, a first latch, a third inverter, and a second latch. The third inverter and the fifth inverter include first transistors of a first type formed between a first power contact and a second power contact supplied with a power supply voltage on first-type fins, and second transistors of a second type formed between a first ground contact and a second ground contact supplied with a ground voltage on second-type fins.
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公开(公告)号：US20160056153A1
公开(公告)日：2016-02-25
申请号：US14829650
申请日：2015-08-19
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jung-Ho DO , SANGHOON BAEK , Sunyoung PARK , Moo-Gyu BAE , TAEJOONG SONG
IPC: H01L27/088 , H01L29/06 , H01L23/522 , H01L27/02 , H01L23/535
CPC classification number: H01L27/088 , H01L27/0207 , H01L27/0886 , H01L27/092 , H01L27/0924 , H01L27/11807 , H01L29/0642 , H01L2027/11874
Abstract: A semiconductor device includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a third gate structure extending in the first direction and provided between the first and second gate structures, a first contact connected to the first gate structure and having a first width in the second direction, a second contact connected to the second gate structure and having a second width in the second direction, and a third contact connected to the third gate structure and having a third width in the second direction. The first, second, and third contacts may be aligned with each other in the second direction to constitute one row. The first and second widths may be greater than the third width.
Abstract translation: 半导体器件包括在第一方向上延伸并且沿与第一方向相交的第二方向彼此间隔开的第一和第二栅极结构，在第一方向上延伸并设置在第一和第二栅极结构之间的第三栅极结构， 连接到第一栅极结构并且具有在第二方向上的第一宽度的第二接触，连接到第二栅极结构并且在第二方向上具有第二宽度的第二接触，以及连接到第三栅极结构并具有第三栅极结构的第三接触 宽度在第二个方向。 第一，第二和第三触点可以在第二方向上彼此对准以构成一行。 第一和第二宽度可以大于第三宽度。
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Patent Agency Ranking
公开(公告)号：US20200152640A1
公开(公告)日：2020-05-14
申请号：US16725155
申请日：2019-12-23
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： JUNG-HO DO , SEUNGYOUNG LEE , JONGHOON JUNG , JINYOUNG LIM , GIYOUNG YANG , SANGHOON BAEK , TAEJOONG SONG
IPC: H01L27/11 , H01L23/522 , H01L49/02 , H01L21/768
Abstract: A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.
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公开(公告)号：US20190164603A1
公开(公告)日：2019-05-30
申请号：US16243796
申请日：2019-01-09
Applicant: Samsung Electronics Co., Ltd.
Inventor： Suk-Soo PYO , HYUNTAEK JUNG , TAEJOONG SONG , BOYOUNG SEO
CPC classification number: G11C13/0064 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C11/1677 , G11C11/1693 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/004 , G11C13/0061 , G11C13/0069 , G11C2013/0054 , G11C2013/0073 , G11C2213/74 , G11C2213/79 , G11C2213/82
Abstract: A nonvolatile memory device includes a first variable resistance element connected to a first bit line, and a first transmission ;ate connected between the first variable resistance element and a first source line. The first transmission gate includes a first insulating layer formed on a well connected to aground voltage, a first n-channel metal oxide semiconductor (NMOS) transistor formed on the first insulating layer and connected to a first word line, a second insulating layer formed on the well, the second insulating layer being in the same layer as the first insulating layer, and a first p-channel metal oxide semiconductor (PMOS) transistor formed on the second insulating layer and connected to a first write word line.
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公开(公告)号：US20180323082A1
公开(公告)日：2018-11-08
申请号：US16032127
申请日：2018-07-11
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： JUNG-HO DO , JONGHOON JUNG , SANGHOON BAEK , SEUNGYOUNG LEE , TAEJOONG SONG , JINYOUNG LIM
IPC: H01L21/3213 , H01L21/8238
CPC classification number: H01L21/32139 , H01L21/823807 , H01L21/823821 , H01L21/823878
Abstract: A method of manufacturing a semiconductor device may include forming active patterns, forming a polygonal mask pattern having a first width and a second width on the active patterns, forming an active region by executing a first etching process using the mask pattern, forming a first cutting mask for removing a first corner rounding in which a width of the active region is the first width, removing the first corner rounding by executing a second etching process using the first cutting mask, forming a second cutting mask for removing a second corner rounding in which the width of the active region is changed from the first width to the second width, and executing a third etching process using the second cutting mask.
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公开(公告)号：US20170148727A1
公开(公告)日：2017-05-25
申请号：US15355159
申请日：2016-11-18
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： JUNG-HO DO , SEUNGYOUNG LEE , JONGHOON JUNG , JINYOUNG LIM , GIYOUNG YANG , SANGHOON BAEK , TAEJOONG SONG
IPC: H01L23/528 , H01L23/532 , H01L27/11 , H01L23/522
Abstract: A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.
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公开(公告)号：US20170148687A1
公开(公告)日：2017-05-25
申请号：US15350716
申请日：2016-11-14
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： JUNG-HO DO , JONGHOON JUNG , SANGHOON BAEK , SEUNGYOUNG LEE , TAEJOONG SONG , JINYOUNG LIM
IPC: H01L21/8238 , H01L21/3213
CPC classification number: H01L21/32139 , H01L21/823807 , H01L21/823821 , H01L21/823878
Abstract: A method of manufacturing a semiconductor device may include forming first trenches that define active patterns extending in a first direction on a substrate, forming first insulating layers filling the first trenches, forming first mask patterns extending in the first direction while having a first width along a second direction perpendicular to the first direction, forming a second mask pattern extending in the first direction while having a second width along the second direction, and forming a second trench that partly defines an active region by executing a first etching process that etches the active patterns and the first insulating layer using the first mask patterns and the second mask pattern.
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