公开(公告)号：US20220277778A1

公开(公告)日：2022-09-01

申请号：US17507216

申请日：2021-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunji LEE ,  Suk-Soo PYO

IPC: G11C7/10 ,  G11C8/08

Abstract: A nonvolatile memory device including a memory cell array including a plurality of nonvolatile memory cells and a row decoder connected with the memory cell array through wordlines may be provided. The row decoder may be configured to precharge a first wordline corresponding to a first row address from among the wordlines, in response to receiving the first row address together with a first command, and maintain a precharge state of the first wordline, in response to receiving a second row address being identical to the first row address together with a second command following the first command.

公开(公告)号：US20200312396A1

公开(公告)日：2020-10-01

申请号：US16814678

申请日：2020-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suk-Soo PYO ,  Hyun Taek JUNG

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02

Abstract: A nonvolatile memory device may comprise a memory cell comprising a first variable resistor having one end connected to a first node, and the other end connected to a second node through a cell transistor; and a reference cell comprising a second variable resistor having one end connected to a third node, and the other end connected to a fourth node through a reference cell transistor, wherein gates of the cell transistor and the reference cell transistor are connected to a word line. Directions of a first read current flowing in the memory cell and a direction of a second read current flowing in the reference cell are opposite to each other.

公开(公告)号：US20200090724A1

公开(公告)日：2020-03-19

申请号：US16390170

申请日：2019-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Artur Antonyan ,  Hyuntaek JUNG ,  Suk-Soo PYO

IPC: G11C11/16

Abstract: A memory device including a normal memory cell array including a first magneto-resistance memory cell that is connected to a first bit line, a first source line, and a first word line, and configured to receive a selection voltage through the first word line, a monitor memory cell array including a second magneto-resistance memory cell that is connected to a first signal line and a second signal line, a gate of a cell transistor of which is configured to receive a non-selection voltage, and a body bias generator configured to sense a leakage current flowing through the first signal line and control a body voltage provided to each of a body of a cell transistor of the first magneto-resistance memory cell and a body of the cell transistor of the second magneto-resistance memory cell based on the leakage current may be provided.

公开(公告)号：US20190164603A1

公开(公告)日：2019-05-30

申请号：US16243796

申请日：2019-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suk-Soo PYO ,  HYUNTAEK JUNG ,  TAEJOONG SONG ,  BOYOUNG SEO

IPC: G11C13/00 ,  G11C11/16

CPC classification number: G11C13/0064 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1677 ,  G11C11/1693 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82

Abstract: A nonvolatile memory device includes a first variable resistance element connected to a first bit line, and a first transmission ;ate connected between the first variable resistance element and a first source line. The first transmission gate includes a first insulating layer formed on a well connected to aground voltage, a first n-channel metal oxide semiconductor (NMOS) transistor formed on the first insulating layer and connected to a first word line, a second insulating layer formed on the well, the second insulating layer being in the same layer as the first insulating layer, and a first p-channel metal oxide semiconductor (PMOS) transistor formed on the second insulating layer and connected to a first write word line.