公开(公告)号：US20230154517A1

公开(公告)日：2023-05-18

申请号：US17894554

申请日：2022-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuseong KANG ,  Hyuntaek JUNG

IPC: G11C11/16 ,  G11C8/10

CPC classification number: G11C11/1675 ,  G11C11/1655 ,  G11C11/1657 ,  G11C8/10

Abstract: A memory device including a memory cell array including a first sub memory cell array including a first memory cell and a second sub memory cell array including a second memory cell, a merged write driver including a first write circuit receiving n-bit data (n being a natural number ≥2) through a write input/output line, outputting a first write voltage to a merged node in response to a first data bit of the n-bit data, and outputting a second write voltage to the merged node in response to a second data bit of the n-bit data, and a column decoder including a first column multiplexer applying a first voltage of the merged node corresponding to the first data bit to the first memory cell and a second column multiplexer applying a second voltage of the merged node corresponding to the second data bit to the second memory cell.

公开(公告)号：US20250149097A1

公开(公告)日：2025-05-08

申请号：US18753659

申请日：2024-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byeonghoon CHOI ,  Myeonghee OH ,  Hyuntaek JUNG ,  Hanbyul CHOI

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

Abstract: A memory device includes a memory cell array including a plurality of memory cells, respectively connected to a plurality of bitlines, a first multiplexer including a plurality of transistors connected to the plurality of bitlines, a reference circuit that generates reference current, a decoding circuit that transmits the reference current to the first multiplexer, and a control logic circuit connected to the reference circuit and the decoding circuit. The control logic circuit controls control the decoding circuit to apply the reference current to transistors, connected to each of at least two bitlines, such that predetermined first current flows through the at least two bitlines.

公开(公告)号：US20200090724A1

公开(公告)日：2020-03-19

申请号：US16390170

申请日：2019-04-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Artur Antonyan ,  Hyuntaek JUNG ,  Suk-Soo PYO

IPC: G11C11/16

Abstract: A memory device including a normal memory cell array including a first magneto-resistance memory cell that is connected to a first bit line, a first source line, and a first word line, and configured to receive a selection voltage through the first word line, a monitor memory cell array including a second magneto-resistance memory cell that is connected to a first signal line and a second signal line, a gate of a cell transistor of which is configured to receive a non-selection voltage, and a body bias generator configured to sense a leakage current flowing through the first signal line and control a body voltage provided to each of a body of a cell transistor of the first magneto-resistance memory cell and a body of the cell transistor of the second magneto-resistance memory cell based on the leakage current may be provided.