公开(公告)号：US20250149097A1

公开(公告)日：2025-05-08

申请号：US18753659

申请日：2024-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byeonghoon CHOI ,  Myeonghee OH ,  Hyuntaek JUNG ,  Hanbyul CHOI

IPC: G11C16/24 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10

Abstract: A memory device includes a memory cell array including a plurality of memory cells, respectively connected to a plurality of bitlines, a first multiplexer including a plurality of transistors connected to the plurality of bitlines, a reference circuit that generates reference current, a decoding circuit that transmits the reference current to the first multiplexer, and a control logic circuit connected to the reference circuit and the decoding circuit. The control logic circuit controls control the decoding circuit to apply the reference current to transistors, connected to each of at least two bitlines, such that predetermined first current flows through the at least two bitlines.