公开(公告)号：US20230154517A1

公开(公告)日：2023-05-18

申请号：US17894554

申请日：2022-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuseong KANG ,  Hyuntaek JUNG

IPC: G11C11/16 ,  G11C8/10

CPC classification number: G11C11/1675 ,  G11C11/1655 ,  G11C11/1657 ,  G11C8/10

Abstract: A memory device including a memory cell array including a first sub memory cell array including a first memory cell and a second sub memory cell array including a second memory cell, a merged write driver including a first write circuit receiving n-bit data (n being a natural number ≥2) through a write input/output line, outputting a first write voltage to a merged node in response to a first data bit of the n-bit data, and outputting a second write voltage to the merged node in response to a second data bit of the n-bit data, and a column decoder including a first column multiplexer applying a first voltage of the merged node corresponding to the first data bit to the first memory cell and a second column multiplexer applying a second voltage of the merged node corresponding to the second data bit to the second memory cell.

公开(公告)号：US20230178132A1

公开(公告)日：2023-06-08

申请号：US17870545

申请日：2022-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuseong KANG

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C11/1655 ,  G11C11/1657

Abstract: A semiconductor device includes a first memory cell array including a plurality of first memory cells, a plurality of first reference cells and a plurality of first dummy cells, a second memory cell array including a plurality of second memory cells, a plurality of second reference cells and a plurality of second dummy cells, an input/output circuit provided between the first memory cell array and the second memory cell array, a first column decoder connected between the first memory cell array and the input/output circuit and a second column decoder connected between the second memory cell array and the input/output circuit. The second column decoder connects one of the plurality of second dummy cells and the plurality of second memory cells to a selected sense amplifier of the input/output circuit, when the first column decoder connects a selected first memory cell to the selected sense amplifier.

公开(公告)号：US20250166685A1

公开(公告)日：2025-05-22

申请号：US18900110

申请日：2024-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuseong KANG ,  Dohui KIM

IPC: G11C11/16

Abstract: Disclosed is a method and a memory device implementing the method. The method may include searching for a number of fail bits of output data output from a memory cell array of the memory device; determining a coarse offset reference resistance; searching for a number of fail bits of a first output data within a first reference resistance range based on the coarse offset reference resistance, determining a first fine offset reference resistance; searching for a number of fail bits of the second output data within a second reference resistance range based on the coarse offset reference resistance, determining a second fine offset reference resistance; and adjusting a reference resistance for a read operation using the coarse offset reference resistance and fine offset reference resistances, the fine offset reference resistances comprising resistances from the first fine offset reference resistance to the second fine offset reference resistance.

公开(公告)号：US20240404597A1

公开(公告)日：2024-12-05

申请号：US18405564

申请日：2024-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyuseong KANG

IPC: G11C13/00 ,  G11C29/52

Abstract: A memory device includes a memory cell array including memory cells, a row decoder, a column decoder, a sense amplifier that reads data stored in a memory cell by detecting a difference between a source line voltage and a reference voltage during a read operation, and a control logic including a read offset compensator that receives output data from the sense amplifier and performs an offset reference resistance compensation operation. The read offset compensator compares a number of error bits of the output data with a threshold value, performs the offset reference resistance compensation operation based on a result of the comparison, calculates a local resistance for compensating an offset reference resistance for the sense amplifier during the offset reference resistance compensation operation, and adjusts a reference resistance for the sense amplifier based on the local resistance during the read operation.