公开(公告)号：US20160056155A1

公开(公告)日：2016-02-25

申请号：US14833983

申请日：2015-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE-HO PARK ,  TAEJOONG SON ,  SANGHOON BAEK ,  JINTAE KIM ,  GIYOUNG YANG ,  HYOSIG WON

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/0642 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41758 ,  H01L29/41791

Abstract: A semiconductor device includes a substrate having an active region, a gate structure intersecting the active region and extending in a first direction parallel to a top surface of the substrate, a first source/drain region and a second source/drain region disposed in the active region at both sides of the gate structure, respectively, and a first modified contact and a second modified contact in contact with the first source/drain region and the second source/drain region, respectively. The distance between the gate structure and the first modified contact is smaller than the distance between the gate structure and the second modified contact.

Abstract translation: 半导体器件包括具有有源区的衬底，与有源区相交且在平行于衬底顶表面的第一方向上延伸的栅极结构，设置在有源区中的第一源极/漏极区和第二源极/漏极区 分别与第一源极/漏极区域和第二源极/漏极区域接触的第一修改触点和第二修改触点。 栅极结构和第一改性接触之间的距离小于栅极结构和第二改性接触之间的距离。

公开(公告)号：US20180174861A1

公开(公告)日：2018-06-21

申请号：US15899686

申请日：2018-02-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HO DO ,  JONGHOON JUNG ,  SANGHOON BAEK ,  SEUNGYOUNG LEE ,  TAEJOONG SONG ,  JINYOUNG LIM

IPC: H01L21/3213 ,  H01L21/8238

CPC classification number: H01L21/32139 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878

Abstract: A method of manufacturing a semiconductor device may include forming first trenches that define active patterns extending in a first direction on a substrate, forming first insulating layers filling the first trenches, forming first mask patterns extending in the first direction while having a first width along a second direction perpendicular to the first direction, forming a second mask pattern extending in the first direction while having a second width along the second direction, and forming a second trench that partly defines an active region by executing a first etching process that etches the active patterns and the first insulating layer using the first mask patterns and the second mask pattern.

公开(公告)号：US20160056153A1

公开(公告)日：2016-02-25

申请号：US14829650

申请日：2015-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ho DO ,  SANGHOON BAEK ,  Sunyoung PARK ,  Moo-Gyu BAE ,  TAEJOONG SONG

IPC: H01L27/088 ,  H01L29/06 ,  H01L23/522 ,  H01L27/02 ,  H01L23/535

CPC classification number: H01L27/088 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/0642 ,  H01L2027/11874

Abstract: A semiconductor device includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a third gate structure extending in the first direction and provided between the first and second gate structures, a first contact connected to the first gate structure and having a first width in the second direction, a second contact connected to the second gate structure and having a second width in the second direction, and a third contact connected to the third gate structure and having a third width in the second direction. The first, second, and third contacts may be aligned with each other in the second direction to constitute one row. The first and second widths may be greater than the third width.

Abstract translation: 半导体器件包括在第一方向上延伸并且沿与第一方向相交的第二方向彼此间隔开的第一和第二栅极结构，在第一方向上延伸并设置在第一和第二栅极结构之间的第三栅极结构， 连接到第一栅极结构并且具有在第二方向上的第一宽度的第二接触，连接到第二栅极结构并且在第二方向上具有第二宽度的第二接触，以及连接到第三栅极结构并具有第三栅极结构的第三接触 宽度在第二个方向。 第一，第二和第三触点可以在第二方向上彼此对准以构成一行。 第一和第二宽度可以大于第三宽度。

公开(公告)号：US20210165947A1

公开(公告)日：2021-06-03

申请号：US17087915

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAE-HO PARK ,  SANGHOON BAEK ,  JI SU YU ,  HYEON GYU YOU ,  SEUNG YOUNG LEE ,  SEUNG MAN LIM ,  MIN JAE JEONG ,  JONG HOON JUNG

IPC: G06F30/392 ,  H01L27/02 ,  G06F30/394

Abstract: A layout method is provided. The layout method may include placing first and second standard cells from a standard cell library, interconnecting the placed standard cells to generate a layout draft, confirming placement and routing at a boundary region between the interconnected standard cells, and revising the layout draft based on the confirmation. Each of the standard cells includes, in part, a conductive line that extends in the first direction and is interconnected to an adjacent standard cell through a source/drain via. To confirm the placement and routing, a first spaced distance from a tip of one of the conductive lines to a tip of the other conductive line, and a second spaced distance from the tip of the first conductive line to the cell boundary are compared with preset threshold values. Revising the layout draft may include adjusting a tip position of one of the conductive lines.

公开(公告)号：US20180173836A1

公开(公告)日：2018-06-21

申请号：US15896415

申请日：2018-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAEJOONG SONG ,  SANGHOON BAEK ,  SUNGWE CHO ,  JUNG-HO DO ,  GIYOUNG YANG ,  JINYOUNG LIM

IPC: G06F17/50 ,  H01L27/118 ,  H01L27/02

CPC classification number: G06F17/5077 ,  H01L27/0207 ,  H01L27/11807

Abstract: A method of designing a semiconductor device includes preparing a standard cell layout including a layout out a preliminary pin pattern in at least one interconnection layout, performing a routing step to connect the preliminary pin pattern to a high-level interconnection layout, and generating a pin pattern in the interconnection layout, based on hitting information obtained at the completion of the routing step. The pin pattern is smaller than the preliminary pin pattern.

公开(公告)号：US20210104463A1

公开(公告)日：2021-04-08

申请号：US16946491

申请日：2020-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： SEUNGYOUNG LEE ,  SANGHOON BAEK

IPC: H01L23/528 ,  G06F30/3953 ,  G06F30/392 ,  H01L23/522

Abstract: A semiconductor device includes: a device layer including first and second active patterns, extending in a first direction on a substrate and adjacent to each other, and a plurality of gate electrodes extending in a second direction, intersecting the first direction, on the substrate and crossing the first and second active patterns; a lower wiring layer on the device layer, and including first and second lower wiring patterns extending in the first direction, located on the first and second active patterns, respectively, and connected to the plurality of gate electrodes; and an upper wiring layer on the lower wiring layer, and having first and second upper vias on the first and second lower wiring patterns, respectively, and first and second upper wiring patterns extending in the second direction. The first upper wiring pattern is connected to the first upper via without being connected to the second upper via and the second upper wiring pattern is connected to the second upper via without being connected to the first upper via.

公开(公告)号：US20170110372A1

公开(公告)日：2017-04-20

申请号：US15392725

申请日：2016-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGHOON BAEK ,  JAE-HO PARK ,  SEOLUN YANG ,  TAEJOONG SONG ,  SANG-KYU OH

IPC: H01L21/8234 ,  H01L21/308 ,  H01L29/78 ,  H01L27/02 ,  H01L27/108 ,  H01L27/11 ,  H01L21/027 ,  H01L21/762

CPC classification number: H01L21/823431 ,  H01L21/0274 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7851

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

公开(公告)号：US20160056083A1

公开(公告)日：2016-02-25

申请号：US14833922

申请日：2015-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HO DO ,  SANGHOON BAEK ,  SUNYOUNG PARK ,  SANG-KYU OH ,  JINTAE KIM ,  HYOSIG WON

IPC: H01L21/8234 ,  H01L21/027 ,  H01L29/66 ,  H01L29/417 ,  H01L21/321 ,  H01L21/28 ,  H01L21/768

CPC classification number: H01L21/823475 ,  H01L21/0274 ,  H01L21/28008 ,  H01L21/32115 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76877 ,  H01L21/76895 ,  H01L21/76897 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L29/41758 ,  H01L29/66568

Abstract: A method of manufacturing a semiconductor device includes forming an active pattern and a gate electrode crossing the active pattern on a substrate, forming a first contact connected to the active pattern at a side of the gate electrode, forming a second contact connected to the gate electrode, and forming a third contact connected to the first contact at the side of the gate electrode. The third contact is formed using a photomask different from that used to form the first contact. A bottom surface of the third contact is disposed at a level in the device lower than the level of a top surface of the first contact.

Abstract translation: 一种制造半导体器件的方法包括：在基板上形成与有源图案交叉的有源图案和栅电极，在栅电极侧形成连接到有源图案的第一触点，形成连接到栅电极的第二触点 并且形成在栅电极侧与第一接触连接的第三触点。 使用不同于用于形成第一接触的光掩模形成第三接触。 第三触点的底表面设置在器件中比第一触点的顶表面的水平低的水平面上。

公开(公告)号：US20200152640A1

公开(公告)日：2020-05-14

申请号：US16725155

申请日：2019-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HO DO ,  SEUNGYOUNG LEE ,  JONGHOON JUNG ,  JINYOUNG LIM ,  GIYOUNG YANG ,  SANGHOON BAEK ,  TAEJOONG SONG

IPC: H01L27/11 ,  H01L23/522 ,  H01L49/02 ,  H01L21/768

Abstract: A semiconductor device including: a conductor disposed on a substrate; a first contact disposed on the conductor; a second contact having a first portion disposed on the first contact and a second portion protruded away from the first portion in a direction parallel to the substrate, wherein the first and second contacts are disposed in an insulating layer; a via disposed on the insulating layer and the second portion of the second contact; and a metal line disposed on the via.

公开(公告)号：US20180323082A1

公开(公告)日：2018-11-08

申请号：US16032127

申请日：2018-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG-HO DO ,  JONGHOON JUNG ,  SANGHOON BAEK ,  SEUNGYOUNG LEE ,  TAEJOONG SONG ,  JINYOUNG LIM

IPC: H01L21/3213 ,  H01L21/8238

CPC classification number: H01L21/32139 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878

Abstract: A method of manufacturing a semiconductor device may include forming active patterns, forming a polygonal mask pattern having a first width and a second width on the active patterns, forming an active region by executing a first etching process using the mask pattern, forming a first cutting mask for removing a first corner rounding in which a width of the active region is the first width, removing the first corner rounding by executing a second etching process using the first cutting mask, forming a second cutting mask for removing a second corner rounding in which the width of the active region is changed from the first width to the second width, and executing a third etching process using the second cutting mask.