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    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SAME 有权

    公开(公告)号：US20210104463A1

    公开(公告)日：2021-04-08

    申请号：US16946491

    申请日：2020-06-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SEUNGYOUNG LEE ,  SANGHOON BAEK

    IPC: H01L23/528 ,  G06F30/3953 ,  G06F30/392 ,  H01L23/522

    Abstract: A semiconductor device includes: a device layer including first and second active patterns, extending in a first direction on a substrate and adjacent to each other, and a plurality of gate electrodes extending in a second direction, intersecting the first direction, on the substrate and crossing the first and second active patterns; a lower wiring layer on the device layer, and including first and second lower wiring patterns extending in the first direction, located on the first and second active patterns, respectively, and connected to the plurality of gate electrodes; and an upper wiring layer on the lower wiring layer, and having first and second upper vias on the first and second lower wiring patterns, respectively, and first and second upper wiring patterns extending in the second direction. The first upper wiring pattern is connected to the first upper via without being connected to the second upper via and the second upper wiring pattern is connected to the second upper via without being connected to the first upper via.

    INTEGRATED CIRCUIT DEVICES INCLUDING A CROSS-COUPLED STRUCTURE
    3.
    发明申请
    INTEGRATED CIRCUIT DEVICES INCLUDING A CROSS-COUPLED STRUCTURE 有权

    公开(公告)号：US20230047840A1

    公开(公告)日：2023-02-16

    申请号：US17503486

    申请日：2021-10-18

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： SEUNGYOUNG LEE ,  SAEHAN PARK

    IPC: H01L29/786 ,  H03B5/12

    Abstract: Cross-coupled structures are provided. Cross-coupled structures may include a first transistor, a second transistor, a third transistor, and a fourth transistor. The first transistor, the second transistor, and the fourth transistor may be spaced apart from each other in a first direction, and the third transistor and the second transistor may be stacked in a second direction that is perpendicular to the first direction. The third transistor and the second transistor may include a common gate structure, a first portion of the common gate structure may be a gate structure of the second transistor, and a second portion of the common gate structure may be a gate structure of the third transistor.

    STACKED INTEGRATED CIRCUIT DEVICES
    5.
    发明申请
    STACKED INTEGRATED CIRCUIT DEVICES 有权

    公开(公告)号：US20220093489A1

    公开(公告)日：2022-03-24

    申请号：US17540303

    申请日：2021-12-02

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JUNG HO DO ,  SEUNGYOUNG LEE

    IPC: H01L23/48 ,  H01L27/02 ,  H01L27/088

    Abstract: Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.

    STACKED INTEGRATED CIRCUIT DEVICES
    6.
    发明申请
    STACKED INTEGRATED CIRCUIT DEVICES 有权

    公开(公告)号：US20210384106A1

    公开(公告)日：2021-12-09

    申请号：US16947241

    申请日：2020-07-24

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： JUNG HO DO ,  SEUNGYOUNG LEE

    IPC: H01L23/48 ,  H01L27/088 ,  H01L27/02

    Abstract: Stacked integrated circuit devices may include standard cells including a first standard cell in a first row and a second standard cell in a second row immediately adjacent to the first row. Each of the standard cells may include an upper transistor and a lower transistor. The upper transistor may include an upper active region, an upper gate structure, and an upper source/drain region. The lower transistor may include a lower active region, a lower gate structure, and a lower source/drain region. Each of the standard cells may also include a power line and a power via electrically connecting the power line to the lower source/drain region. The power via of the first standard cell and the power via of the second standard cell may be aligned with each other along the first direction.

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