公开(公告)号：US20210165947A1

公开(公告)日：2021-06-03

申请号：US17087915

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAE-HO PARK ,  SANGHOON BAEK ,  JI SU YU ,  HYEON GYU YOU ,  SEUNG YOUNG LEE ,  SEUNG MAN LIM ,  MIN JAE JEONG ,  JONG HOON JUNG

IPC: G06F30/392 ,  H01L27/02 ,  G06F30/394

Abstract: A layout method is provided. The layout method may include placing first and second standard cells from a standard cell library, interconnecting the placed standard cells to generate a layout draft, confirming placement and routing at a boundary region between the interconnected standard cells, and revising the layout draft based on the confirmation. Each of the standard cells includes, in part, a conductive line that extends in the first direction and is interconnected to an adjacent standard cell through a source/drain via. To confirm the placement and routing, a first spaced distance from a tip of one of the conductive lines to a tip of the other conductive line, and a second spaced distance from the tip of the first conductive line to the cell boundary are compared with preset threshold values. Revising the layout draft may include adjusting a tip position of one of the conductive lines.

公开(公告)号：US20170110372A1

公开(公告)日：2017-04-20

申请号：US15392725

申请日：2016-12-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SANGHOON BAEK ,  JAE-HO PARK ,  SEOLUN YANG ,  TAEJOONG SONG ,  SANG-KYU OH

IPC: H01L21/8234 ,  H01L21/308 ,  H01L29/78 ,  H01L27/02 ,  H01L27/108 ,  H01L27/11 ,  H01L21/027 ,  H01L21/762

CPC classification number: H01L21/823431 ,  H01L21/0274 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7851

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

公开(公告)号：US20160056155A1

公开(公告)日：2016-02-25

申请号：US14833983

申请日：2015-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE-HO PARK ,  TAEJOONG SON ,  SANGHOON BAEK ,  JINTAE KIM ,  GIYOUNG YANG ,  HYOSIG WON

IPC: H01L27/088 ,  H01L29/417 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/0642 ,  H01L21/768 ,  H01L21/76816 ,  H01L21/823871 ,  H01L27/0207 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/41758 ,  H01L29/41791

Abstract: A semiconductor device includes a substrate having an active region, a gate structure intersecting the active region and extending in a first direction parallel to a top surface of the substrate, a first source/drain region and a second source/drain region disposed in the active region at both sides of the gate structure, respectively, and a first modified contact and a second modified contact in contact with the first source/drain region and the second source/drain region, respectively. The distance between the gate structure and the first modified contact is smaller than the distance between the gate structure and the second modified contact.

Abstract translation: 半导体器件包括具有有源区的衬底，与有源区相交且在平行于衬底顶表面的第一方向上延伸的栅极结构，设置在有源区中的第一源极/漏极区和第二源极/漏极区 分别与第一源极/漏极区域和第二源极/漏极区域接触的第一修改触点和第二修改触点。 栅极结构和第一改性接触之间的距离小于栅极结构和第二改性接触之间的距离。

公开(公告)号：US20140380256A1

公开(公告)日：2014-12-25

申请号：US14258065

申请日：2014-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： TAE-JOONG SONG ,  JAE-HO PARK ,  KWANG-OK JEONG

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G03F1/70 ,  G03F7/0035 ,  G06F17/5068 ,  G06F17/5077

Abstract: A double patterning layout design method comprises defining critical paths comprising a first path and a second path on a schematic circuit, and defining a double patterning layout divided into a first mask layout having a first color and a second mask layout having a second color, the double patterning layout corresponding to the schematic circuit. The defining of the double patterning layout comprises anchoring the critical paths on the schematic circuit.

Abstract translation: 双重图案化布局设计方法包括在原理图电路上定义包括第一路径和第二路径的关键路径，并且限定分成具有第一颜色的第一掩模布局和具有第二颜色的第二掩模布局的双图案布局， 双重图案布局对应于原理图电路。 双重图案化布局的定义包括将关键路径锚定在原理图电路上。