公开(公告)号：US20160056153A1

公开(公告)日：2016-02-25

申请号：US14829650

申请日：2015-08-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-Ho DO ,  SANGHOON BAEK ,  Sunyoung PARK ,  Moo-Gyu BAE ,  TAEJOONG SONG

IPC: H01L27/088 ,  H01L29/06 ,  H01L23/522 ,  H01L27/02 ,  H01L23/535

CPC classification number: H01L27/088 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/11807 ,  H01L29/0642 ,  H01L2027/11874

Abstract: A semiconductor device includes first and second gate structures extending in a first direction and spaced apart from each other in a second direction intersecting the first direction, a third gate structure extending in the first direction and provided between the first and second gate structures, a first contact connected to the first gate structure and having a first width in the second direction, a second contact connected to the second gate structure and having a second width in the second direction, and a third contact connected to the third gate structure and having a third width in the second direction. The first, second, and third contacts may be aligned with each other in the second direction to constitute one row. The first and second widths may be greater than the third width.

Abstract translation: 半导体器件包括在第一方向上延伸并且沿与第一方向相交的第二方向彼此间隔开的第一和第二栅极结构，在第一方向上延伸并设置在第一和第二栅极结构之间的第三栅极结构， 连接到第一栅极结构并且具有在第二方向上的第一宽度的第二接触，连接到第二栅极结构并且在第二方向上具有第二宽度的第二接触，以及连接到第三栅极结构并具有第三栅极结构的第三接触 宽度在第二个方向。 第一，第二和第三触点可以在第二方向上彼此对准以构成一行。 第一和第二宽度可以大于第三宽度。

公开(公告)号：US20170271367A1

公开(公告)日：2017-09-21

申请号：US15612349

申请日：2017-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon BAEK ,  Sang-kyu OH ,  Jung-Ho DO ,  Sun-young PARK ,  Seung-young LEE ,  Hyo-sig WON

IPC: H01L27/118 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/42384 ,  H01L29/6681 ,  H01L29/785 ,  H01L2027/11875

Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.

公开(公告)号：US20170133367A1

公开(公告)日：2017-05-11

申请号：US15416016

申请日：2017-01-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hoon BAEK ,  Sun-Young PARK ,  Sang-Kyu OH ,  Ha-Young KIM ,  Jung-Ho DO ,  Moo-Gyu BAE ,  Seung-Young LEE

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/11 ,  H01L23/528 ,  H01L27/02

CPC classification number: H01L27/088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104

Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

公开(公告)号：US20160085904A1

公开(公告)日：2016-03-24

申请号：US14844420

申请日：2015-09-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejoong SONG ,  Jung-Ho DO ,  Changho HAN

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G01R31/2882 ,  G06F2217/14

Abstract: A semiconductor device and a layout verification method of a semiconductor device are provided. The layout verification method includes forming a plurality of standard cells each having a first type of a cross coupled structure (XC) and a second type of the XC on a substrate of the semiconductor device, forming a plurality of first inverters in which the first type of the XC is activated in the a plurality of the standard cells and a plurality of second inverters in which the second type of the XC is activated in the a plurality of the standard cells and estimating an electrical characteristic of the first type of the XC or the second type of the XC by measuring a magnitude of a signal delay of the plurality of the first inverters or the plurality of the second inverters.

Abstract translation: 提供半导体器件的半导体器件和布局验证方法。 布局验证方法包括在半导体器件的衬底上形成多个标准单元，每个标准单元具有第一类型的交叉耦合结构（XC）和第二类型的XC，形成多个第一反相器，其中第一类型 在多个标准单元中激活XC的多个标准单元以及多个第二反相器，其中第二类型的XC在多个标准单元中被激活并且估计第一类型的XC的电特性或 通过测量多个第一反相器或多个第二反相器的信号延迟的大小来确定第二类型的XC。

公开(公告)号：US20180350838A1

公开(公告)日：2018-12-06

申请号：US16043236

申请日：2018-07-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Ha-Young KIM ,  Jung-Ho DO ,  Sanghoon BAEK ,  Jinyoung LIM ,  Kwangok JEONG

IPC: H01L27/118 ,  H01L21/66 ,  G06F17/50 ,  H01L49/02 ,  H01L27/11582 ,  H01L27/092 ,  H01L27/02 ,  G03F1/36 ,  H01L21/8238

CPC classification number: H01L27/11807 ,  G03F1/36 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/823821 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11582 ,  H01L28/00 ,  H01L2027/11831 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

公开(公告)号：US20180342505A1

公开(公告)日：2018-11-29

申请号：US16037581

申请日：2018-07-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hoon BAEK ,  Sun-Young PARK ,  Sang-Kyu OH ,  Ha-young KIM ,  Jung-Ho DO ,  Moo-Gyu BAE ,  Seung-Young LEE

IPC: H01L27/088 ,  H01L23/528 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/11

CPC classification number: H01L27/088 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/845 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104 ,  H01L27/1211

Abstract: A method is provided. The method includes forming a first to third gate lines on a substrate, the second gate line formed between the first and third gate lines; forming a gate isolation region to cut the first to third gate lines into two first sub gate lines, two second sub gate lines and two third sub gate lines, respectively; forming a first gate contact on one of the two first sub gate lines; forming a second gate contact on the two second sub gate lines; forming a third gate contact on one of the two third sub gate lines; forming a first metal line to connect the first and third gate contacts; and forming a second metal line. The first to third gate lines extend in a first direction, and the gate isolation region extends in a second direction different from the first direction.

公开(公告)号：US20170062475A1

公开(公告)日：2017-03-02

申请号：US15282206

申请日：2016-09-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Ha-Young KIM ,  Jung-Ho DO ,  Sanghoon BAEK ,  Jinyoung LIM ,  Kwangok JEONG

IPC: H01L27/118 ,  G03F1/36 ,  G06F17/50

CPC classification number: H01L27/11807 ,  G03F1/36 ,  G06F17/5045 ,  G06F17/505 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/823821 ,  H01L21/823878 ,  H01L22/20 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11582 ,  H01L28/00 ,  H01L2027/11831 ,  H01L2027/11881

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

公开(公告)号：US20170365593A1

公开(公告)日：2017-12-21

申请号：US15692670

申请日：2017-08-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seungyoung LEE ,  Sanghoon BAEK ,  Jung-Ho DO

IPC: H01L27/02 ,  H01L23/528 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L29/66628 ,  H01L29/7848

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, an insulating layer on the gate electrode, first and second lower vias in the insulating layer, first and second lower metal lines provided on the insulating layer and respectively connected to the first and second lower vias, and first and second upper metal lines provided on and respectively connected to the first and second lower metal lines. When viewed in a plan view, the first lower via is overlapped with the second upper metal line, and the second lower via is overlapped with the first upper metal line.

公开(公告)号：US20200212069A1

公开(公告)日：2020-07-02

申请号：US16817094

申请日：2020-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejoong SONG ,  Ha-Young KIM ,  Jung-Ho DO ,  Sanghoon BAEK ,  Jinyoung LIM ,  Kwangok JEONG

IPC: H01L27/118 ,  H01L27/092 ,  H01L27/02 ,  H01L21/66 ,  H01L21/8238 ,  H01L49/02 ,  H01L27/11582 ,  G03F1/36 ,  G06F30/398 ,  G06F30/394 ,  G06F30/327 ,  G06F30/30

Abstract: A semiconductor device includes a substrate including a first active region and a second active region, the first active region having a conductivity type that is different than a conductivity type of the second active region, and the first active region being spaced apart from the second active region in a first direction, gate electrodes extending in the first direction, the gate electrodes intersecting the first active region and the second active region, a first shallow isolation pattern disposed in an upper portion of the first active region, the first shallow isolation pattern extending in the first direction, and a deep isolation pattern disposed in an upper portion of the second active region, the deep isolation pattern extending in the first direction, and the deep isolation pattern dividing the second active region into a first region and a second region.

公开(公告)号：US20200152627A1

公开(公告)日：2020-05-14

申请号：US16746071

申请日：2020-01-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sang-Hoon BAEK ,  Sun-Young PARK ,  Sang-Kyu OH ,  Ha-young KIM ,  Jung-Ho DO ,  Moo-Gyu BAE ,  Seung-Young LEE

IPC: H01L27/088 ,  H01L27/12 ,  H01L21/84 ,  H01L23/528 ,  H01L21/8234 ,  H01L27/11 ,  H01L27/02

Abstract: A system on chip includes first to third nanowires extending in a second direction, first to third gate lines respectively surrounding the first to third nanowires, each of the first to third gate lines extending in a first direction across the second direction, a gate isolation region cutting the first to third gate lines and extending in the second direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact; and a second metal line electrically connected to the first gate contact.