公开(公告)号：US20200159984A1

公开(公告)日：2020-05-21

申请号：US16750501

申请日：2020-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho DO ,  Jong-hoon JUNG ,  Ji-Su YU ,  Seung-young LEE ,  Tae-joong SONG ,  Jae-boong LEE

IPC: G06F30/398 ,  H01L27/118 ,  H01L27/02 ,  G06F30/392

Abstract: Provided is an integrated circuit including a plurality of standard cells each including a front-end-of-line (FEOL) region and a back-end-of-line (BEOL) region on the FEOL region, the FEOL region including at least one gate line extending in a first horizontal direction. A BEOL region of a first standard cell among the plurality of standard cells includes an eaves section not overlapping an FEOL region of the first standard cell in a vertical direction, the eaves section protruding in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US20200083210A1

公开(公告)日：2020-03-12

申请号：US16685471

申请日：2019-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-young LEE ,  Jong-hoon Jung ,  Myoung-ho Kang ,  Jung-ho Do

IPC: H01L27/02 ,  G11C11/40 ,  H01L23/528 ,  H01L27/105 ,  H01L27/118 ,  G11C11/419

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.

公开(公告)号：US20180365368A1

公开(公告)日：2018-12-20

申请号：US15933958

申请日：2018-03-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jung-ho DO ,  Jong-hoon JUNG ,  Ji-su YU ,  Seung-young LEE ,  Tae-joong SONG ,  Jae-boong LEE

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  H01L27/0207 ,  H01L27/11807

Abstract: Provided is an integrated circuit including a plurality of standard cells each including a front-end-of-line (FEOL) region and a back-end-of-line (BEOL) region on the FEOL region, the FEOL region including at least one gate line extending in a first horizontal direction. A BEOL region of a first standard cell among the plurality of standard cells includes an eaves section not overlapping an FEOL region of the first standard cell in a vertical direction, the eaves section protruding in a second horizontal direction perpendicular to the first horizontal direction.

公开(公告)号：US20170271367A1

公开(公告)日：2017-09-21

申请号：US15612349

申请日：2017-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-hoon BAEK ,  Sang-kyu OH ,  Jung-Ho DO ,  Sun-young PARK ,  Seung-young LEE ,  Hyo-sig WON

IPC: H01L27/118 ,  H01L27/092 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L27/02

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/42384 ,  H01L29/6681 ,  H01L29/785 ,  H01L2027/11875

Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.

公开(公告)号：US20180108646A1

公开(公告)日：2018-04-19

申请号：US15674931

申请日：2017-08-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seung-young LEE ,  Jong-hoon JUNG ,  Myoung-ho KANG ,  Jung-ho DO

IPC: H01L27/02 ,  G11C11/40 ,  H01L27/105 ,  H01L27/118 ,  H01L23/528

Abstract: In one embodiment, the standard cell includes first and second active regions defining an intermediate region between the first and second active regions; and first, second and third gate lines crossing the first and second active regions and crossing the intermediate region. The first gate line is divided into an upper first gate line and a lower first gate line by a first gap insulating layer in the intermediate region, the second gate line is undivided, and the third gate line is divided into an upper third gate line and a lower third gate line by a second gap insulating layer in the intermediate region.