公开(公告)号：US20200303508A1

公开(公告)日：2020-09-24

申请号：US16662258

申请日：2019-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BYUNGEUN YUN ,  Jun-Gu Kang ,  Dong-IL Park ,  Yongsang Jeong

IPC: H01L29/417 ,  H01L27/088 ,  H01L29/423 ,  H01L23/535

Abstract: A semiconductor device includes: a substrate including a first region and a second region; a first gate stack on the first region of the substrate; a first source/drain contact at a first side of the first gate stack, wherein the first source/drain contact is connected to the substrate; a second gate stack on the second region of the substrate; and a second source/drain contact at a first side of the second gate stack, wherein the second source/drain contact is connected to the substrate, wherein a height of the second source/drain contact is greater than a height of the first source/drain contact, and wherein a width of the second source/drain contact is greater than a width of the first source/drain contact.

公开(公告)号：US20200303512A1

公开(公告)日：2020-09-24

申请号：US16595187

申请日：2019-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YEONKWANG LEE ,  Sungmin Kang ,  Kyungmin Kim ,  Minhee Uh ,  Jun-Gu Kang ,  Youngmok Kim

IPC: H01L29/49 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265

Abstract: A semiconductor device includes a substrate, in which a lower semiconductor layer, an insulating gapfill layer, and an upper semiconductor layer are sequentially stacked. A gate structure is disposed on the upper semiconductor layer. A source/drain electrode is disposed on a sidewall of the gate structure. A semiconductor pattern is disposed between the source/drain electrode and the upper semiconductor layer. The gate structure includes a gate electrode and a spacer structure. The spacer structure includes a first spacer pattern, a second spacer pattern, and a third spacer pattern, sequentially disposed on a sidewall of the gate electrode. The semiconductor pattern is extended to a region below a bottom surface of the third spacer pattern and is connected to the second spacer pattern.

公开(公告)号：US20210384304A1

公开(公告)日：2021-12-09

申请号：US17406257

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungeun Yun ,  Jun-Gu Kang ,  Dong-IL Park ,  Yongsang Jeong

IPC: H01L29/417 ,  H01L23/535 ,  H01L29/423 ,  H01L27/088 ,  H01L27/12 ,  H01L23/528 ,  H01L23/522

Abstract: A semiconductor device includes: a substrate including a first region and a second region; a first gate stack on the first region of the substrate; a first source/drain contact at a first side of the first gate stack, wherein the first source/drain contact is connected to the substrate; a second gate stack on the second region of the substrate; and a second source/drain contact at a first side of the second gate stack, wherein the second source/drain contact is connected to the substrate, wherein a height of the second source/drain contact is greater than a height of the first source/drain contact, and wherein a width of the second source/drain contact is greater than a width of the first source/drain contact.

公开(公告)号：US10937882B2

公开(公告)日：2021-03-02

申请号：US16595187

申请日：2019-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonkwang Lee ,  Sungmin Kang ,  Kyungmin Kim ,  Minhee Uh ,  Jun-Gu Kang ,  Youngmok Kim

IPC: H01L29/06 ,  H01L29/49 ,  H01L27/092 ,  H01L27/12 ,  H01L21/265 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device includes a substrate, in which a lower semiconductor layer, an insulating gapfill layer, and an upper semiconductor layer are sequentially stacked. A gate structure is disposed on the upper semiconductor layer. A source/drain electrode is disposed on a sidewall of the gate structure. A semiconductor pattern is disposed between the source/drain electrode and the upper semiconductor layer. The gate structure includes a gate electrode and a spacer structure. The spacer structure includes a first spacer pattern, a second spacer pattern, and a third spacer pattern, sequentially disposed on a sidewall of the gate electrode. The semiconductor pattern is extended to a region below a bottom surface of the third spacer pattern and is connected to the second spacer pattern.

公开(公告)号：US11114533B2

公开(公告)日：2021-09-07

申请号：US16662258

申请日：2019-10-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byungeun Yun ,  Jun-Gu Kang ,  Dong-Il Park ,  Yongsang Jeong

IPC: H01L29/417 ,  H01L23/535 ,  H01L29/423 ,  H01L27/088 ,  H01L27/12 ,  H01L23/528 ,  H01L23/522

Abstract: A semiconductor device includes: a substrate including a first region and a second region; a first gate stack on the first region of the substrate; a first source/drain contact at a first side of the first gate stack, wherein the first source/drain contact is connected to the substrate; a second gate stack on the second region of the substrate; and a second source/drain contact at a first side of the second gate stack, wherein the second source/drain contact is connected to the substrate, wherein a height of the second source/drain contact is greater than a height of the first source/drain contact, and wherein a width of the second source/drain contact is greater than a width of the first source/drain contact.

公开(公告)号：US10014407B2

公开(公告)日：2018-07-03

申请号：US15401176

申请日：2017-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Gu Kang ,  Myoungkyu Park ,  Chulho Chung

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/10 ,  H01L29/161 ,  H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/51 ,  H01L29/06 ,  H01L29/165

CPC classification number: H01L29/7816 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/0653 ,  H01L29/0869 ,  H01L29/0886 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/513 ,  H01L29/66636 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

Abstract: Provided are a semiconductor device and a method of forming the same. The semiconductor device includes an active region defined by an isolation layer. A source region portion, a drain region portion and a channel region are located in the active region. The channel region includes a first portion located close to the source region portion and a second portion having a higher threshold voltage than the first portion.

公开(公告)号：US09299659B2

公开(公告)日：2016-03-29

申请号：US14273272

申请日：2014-05-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun-Gu Kang ,  OhKyum Kwon ,  Sun-Hyun Kim

IPC: H01L23/52 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76808 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device is manufactured by forming a lower structure on a substrate including first and second regions, simultaneously forming a first interconnection on the lower structure of the first region and a first portion of a second interconnection on the lower structure of the second region, forming a first interlayer insulating layer on the first interconnection and on the first portion of the second interconnection, forming a trench exposing a top surface of the first portion of the second interconnection in the first interlayer insulating layer, and forming a second portion of the second interconnection in the trench. Related structures are also disclosed.

Abstract translation: 通过在包括第一和第二区域的基板上形成下部结构来制造半导体器件，同时在第一区域的下部结构上形成第一互连和在第二区域的下部结构上形成第二互连的第一部分，形成 在所述第一互连上和所述第二互连的所述第一部分上的第一层间绝缘层，形成在所述第一层间绝缘层中露出所述第二互连的第一部分的顶表面的沟槽，以及形成所述第二互连的第二部分 在沟里。 还公开了相关结构。

公开(公告)号：US20140353820A1

公开(公告)日：2014-12-04

申请号：US14199539

申请日：2014-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun Yu ,  Sang-Hoon Park ,  Jun-Gu Kang ,  Oh-Kyum Kwon ,  Sun-Hyun Kim

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03602 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05541 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13144 ,  H01L2924/381 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/04941 ,  H01L2924/00012 ,  H01L2924/207

Abstract: Semiconductor device and method for fabricating the same are provided. The semiconductor device comprises a first metal wiring line, a chip pad which is electrically connected with the first metal wiring line and has a first width, a passivation layer which encloses the chip pad and includes a contact hole, a first barrier pattern formed on a side wall of the contact hole and a top surface of the passivation layer, a contact filling the contact hole on the first barrier pattern, and a bump, which is formed of the same material as the contact, has a second width which is smaller than the first width, and is overlaid with the first metal wiring line and the chip pad, the bump being entirely overlapped with the chip pad.

Abstract translation: 提供半导体装置及其制造方法。 半导体器件包括第一金属布线，与第一金属布线电连接并具有第一宽度的芯片焊盘，封装芯片焊盘并包括接触孔的钝化层，形成在第一金属布线 接触孔的侧壁和钝化层的上表面，填充第一阻挡图案上的接触孔的接触部和由与接触件相同的材料形成的凸块具有小于第二宽度的第二宽度 第一宽度，并且与第一金属布线和芯片焊盘重叠，凸块与芯片焊盘完全重叠。