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    SEMICONDUCTOR DEVICES INCLUDING MULTIPLE INTERCONNECTION STRUCTURES AND METHODS OF MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING MULTIPLE INTERCONNECTION STRUCTURES AND METHODS OF MANUFACTURING THE SAME 有权
    包括多个互连结构的半导体器件及其制造方法

    公开(公告)号：US20150048512A1

    公开(公告)日：2015-02-19

    申请号：US14273272

    申请日：2014-05-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jun-Gu KANG ,  OhKyum Kwon ,  Sun-Hyun Kim

    IPC: H01L23/535 ,  H01L21/768

    CPC classification number: H01L23/5283 ,  H01L21/76808 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device is manufactured by forming a lower structure on a substrate including first and second regions, simultaneously forming a first interconnection on the lower structure of the first region and a first portion of a second interconnection on the lower structure of the second region, forming a first interlayer insulating layer on the first interconnection and on the first portion of the second interconnection, forming a trench exposing a top surface of the first portion of the second interconnection in the first interlayer insulating layer, and forming a second portion of the second interconnection in the trench. Related structures are also disclosed.

    Abstract translation: 通过在包括第一和第二区域的基板上形成下部结构来制造半导体器件，同时在第一区域的下部结构上形成第一互连和在第二区域的下部结构上形成第二互连的第一部分，形成 在所述第一互连上和所述第二互连的所述第一部分上的第一层间绝缘层，形成在所述第一层间绝缘层中露出所述第二互连的第一部分的顶表面的沟槽，以及形成所述第二互连的第二部分 在沟里。 还公开了相关结构。

    Semiconductor devices including multiple interconnection structures
    4.
    发明授权
    Semiconductor devices including multiple interconnection structures 有权
    包括多个互连结构的半导体器件

    公开(公告)号：US09299659B2

    公开(公告)日：2016-03-29

    申请号：US14273272

    申请日：2014-05-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jun-Gu Kang ,  OhKyum Kwon ,  Sun-Hyun Kim

    IPC: H01L23/52 ,  H01L23/528 ,  H01L23/535 ,  H01L21/768 ,  H01L23/532

    CPC classification number: H01L23/5283 ,  H01L21/76808 ,  H01L21/76838 ,  H01L21/76877 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A semiconductor device is manufactured by forming a lower structure on a substrate including first and second regions, simultaneously forming a first interconnection on the lower structure of the first region and a first portion of a second interconnection on the lower structure of the second region, forming a first interlayer insulating layer on the first interconnection and on the first portion of the second interconnection, forming a trench exposing a top surface of the first portion of the second interconnection in the first interlayer insulating layer, and forming a second portion of the second interconnection in the trench. Related structures are also disclosed.

    Abstract translation: 通过在包括第一和第二区域的基板上形成下部结构来制造半导体器件，同时在第一区域的下部结构上形成第一互连和在第二区域的下部结构上形成第二互连的第一部分，形成 在所述第一互连上和所述第二互连的所述第一部分上的第一层间绝缘层，形成在所述第一层间绝缘层中露出所述第二互连的第一部分的顶表面的沟槽，以及形成所述第二互连的第二部分 在沟里。 还公开了相关结构。

    Semiconductor device including a through contact extending between sub-chips and method of fabricating the same
    7.
    发明授权
    Semiconductor device including a through contact extending between sub-chips and method of fabricating the same 有权

    公开(公告)号：US11049814B2

    公开(公告)日：2021-06-29

    申请号：US16553018

    申请日：2019-08-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Euiyeol Kim ,  Sun-Hyun Kim ,  Heewoo Park

    IPC: H01L23/538 ,  H01L23/522 ,  H01L21/768 ,  H01L25/065 ,  H01L23/528

    Abstract: A semiconductor device may include first and second sub chips stacked sequentially and a through contact electrically connecting the first and second sub chips to each other. Each of the first and second sub chips may include a substrate and a plurality of interconnection lines, which are interposed between the substrates. The interconnection lines of the second sub chip may include first and second interconnection lines having first and second openings, respectively, which are horizontally offset from each other. The through contact may be extended from the substrate of the second sub chip toward the first sub chip and may include an auxiliary contact, which is extended toward the first sub chip through the first and second openings and has a bottom surface higher than a top surface of the uppermost one of the interconnection lines of the first sub chip.

    Image sensors
    8.
    发明授权
    Image sensors 有权

    公开(公告)号：US10991742B2

    公开(公告)日：2021-04-27

    申请号：US16558820

    申请日：2019-09-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dae-han Han ,  Sun-Hyun Kim ,  Han-seok Kim ,  Chung-ho Song ,  Gyeong-hee Lee ,  Hee-geun Jeong

    IPC: H01L27/146 ,  H01L21/00 ,  H01L23/522

    Abstract: An image sensor includes a semiconductor substrate having a first surface and a second surface, a pixel element isolation film extending through an interior of the semiconductor substrate and defining a plurality of active pixels in the semiconductor substrate, and a dummy element isolation film extending through the interior of the semiconductor substrate and extending along at least one side of the active pixels in a plan view and defining a plurality of dummy pixels in the semiconductor substrate. The pixel element isolation film may have a first end that is substantially coplanar with the first surface and has a first width in a first direction parallel to the first surface, and the dummy element isolation film has a first end that is substantially coplanar with the first surface and has a second width that is greater than the first width of the pixel element isolation film.

    Semiconductor devices
    9.
    发明授权
    Semiconductor devices 有权

    公开(公告)号：US10186541B2

    公开(公告)日：2019-01-22

    申请号：US15224095

    申请日：2016-07-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sun-Hyun Kim ,  Kyeongjae Byeon ,  Chungho Song ,  Heegeun Jeong

    IPC: H01L27/146

    Abstract: A semiconductor device includes a pad disposed on a semiconductor layer, an insulating layer disposed between the semiconductor layer and the pad, a through-via penetrating the semiconductor layer and the insulating layer so as to be connected to the pad, and an isolation layer penetrating the semiconductor layer and surrounding the pad when viewed from a plan view.

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