公开(公告)号：US20170040358A1

公开(公告)日：2017-02-09

申请号：US15224095

申请日：2016-07-29

Applicant: Samsung Electronics Co. , Ltd.

Inventor： Sun-Hyun KIM ,  Kyeongjae Byeon ,  Chungho Song ,  Heegeun Jeong

IPC: H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14689

Abstract: A semiconductor device includes a pad disposed on a semiconductor layer, an insulating layer disposed between the semiconductor layer and the pad, a through-via penetrating the semiconductor layer and the insulating layer so as to be connected to the pad, and an isolation layer penetrating the semiconductor layer and surrounding the pad when viewed from a plan view.

Abstract translation: 半导体器件包括设置在半导体层上的焊盘，设置在半导体层和焊盘之间的绝缘层，穿透半导体层和绝缘层的贯通孔，以连接到焊盘，并且隔离层穿透 半导体层并且从俯视图观察时围绕该衬垫。

公开(公告)号：US12272704B2

公开(公告)日：2025-04-08

申请号：US17744045

申请日：2022-05-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyeongjae Byeon ,  Jinyoung Kim ,  Seungjoo Nah ,  Heegeun Jeong

IPC: H01L27/146

Abstract: An image sensor includes a substrate including a first region and a second region surrounding the first region, a light sensing element in the substrate, a planarization layer on the light sensing element, a color filter array layer including color filters on the planarization layer on the first region of the substrate, a light blocking metal pattern on the planarization layer on the second region of the substrate, a dummy color filter layer on the light blocking metal pattern on a portion of the second region adjacent to the first region of the substrate, and microlens on the color filter array layer. Active pixels are in the first region, and optical black (OB) pixels are in the second region.

公开(公告)号：US10186541B2

公开(公告)日：2019-01-22

申请号：US15224095

申请日：2016-07-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Hyun Kim ,  Kyeongjae Byeon ,  Chungho Song ,  Heegeun Jeong

IPC: H01L27/146

Abstract: A semiconductor device includes a pad disposed on a semiconductor layer, an insulating layer disposed between the semiconductor layer and the pad, a through-via penetrating the semiconductor layer and the insulating layer so as to be connected to the pad, and an isolation layer penetrating the semiconductor layer and surrounding the pad when viewed from a plan view.