公开(公告)号：US20140353820A1

公开(公告)日：2014-12-04

申请号：US14199539

申请日：2014-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun Yu ,  Sang-Hoon Park ,  Jun-Gu Kang ,  Oh-Kyum Kwon ,  Sun-Hyun Kim

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03602 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05541 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13144 ,  H01L2924/381 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/04941 ,  H01L2924/00012 ,  H01L2924/207

Abstract: Semiconductor device and method for fabricating the same are provided. The semiconductor device comprises a first metal wiring line, a chip pad which is electrically connected with the first metal wiring line and has a first width, a passivation layer which encloses the chip pad and includes a contact hole, a first barrier pattern formed on a side wall of the contact hole and a top surface of the passivation layer, a contact filling the contact hole on the first barrier pattern, and a bump, which is formed of the same material as the contact, has a second width which is smaller than the first width, and is overlaid with the first metal wiring line and the chip pad, the bump being entirely overlapped with the chip pad.

Abstract translation: 提供半导体装置及其制造方法。 半导体器件包括第一金属布线，与第一金属布线电连接并具有第一宽度的芯片焊盘，封装芯片焊盘并包括接触孔的钝化层，形成在第一金属布线 接触孔的侧壁和钝化层的上表面，填充第一阻挡图案上的接触孔的接触部和由与接触件相同的材料形成的凸块具有小于第二宽度的第二宽度 第一宽度，并且与第一金属布线和芯片焊盘重叠，凸块与芯片焊盘完全重叠。