公开(公告)号：US09825033B2

公开(公告)日：2017-11-21

申请号：US15196400

申请日：2016-06-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Oh-Kyum Kwon ,  Myoung-Kyu Park ,  Chul-Ho Chung

IPC: H01L21/70 ,  H01L27/092 ,  H01L29/161 ,  H01L29/10 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/8256

CPC classification number: H01L27/0922 ,  H01L21/02532 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823857 ,  H01L21/823892 ,  H01L21/8256 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1079 ,  H01L29/161 ,  H01L29/42364 ,  H01L29/66651 ,  H01L29/7833

Abstract: An integrated circuit device includes a substrate including a first region and a second region, a first transistor in the first region, the first transistor being an N-type transistor and including a first silicon-germanium layer on the substrate, and a first gate electrode on the first silicon-germanium layer, and a second transistor in the second region and including a second gate electrode, the second transistor not having a silicon-germanium layer between the substrate and the second gate electrode.

公开(公告)号：US08987797B2

公开(公告)日：2015-03-24

申请号：US14050744

申请日：2013-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Oh-Kyum Kwon ,  Tae-Jung Lee ,  Kyoung-Eun Uhm ,  Byung-Sun Kim

IPC: H01L27/108 ,  H01L27/11 ,  H01L29/78 ,  H01L27/115 ,  H01L29/94

CPC classification number: H01L29/78 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11558 ,  H01L29/94

Abstract: A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region.

Abstract translation: 非易失性存储器件具有通过器件隔离层在衬底中限定的第一有源区和第二有源区，设置在第一有源区上并包括第一电极图的金属氧化物半导体场效应晶体管（MOSFET） 金属氧化物硅（MOS）电容器，其设置在第二有源区并且包括第二电极图案，并且其中第一电极图案在MOSFET的沟道的宽度方向上比第一有源区域窄。

公开(公告)号：US20140353820A1

公开(公告)日：2014-12-04

申请号：US14199539

申请日：2014-03-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun Yu ,  Sang-Hoon Park ,  Jun-Gu Kang ,  Oh-Kyum Kwon ,  Sun-Hyun Kim

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L23/3192 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0345 ,  H01L2224/03602 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05005 ,  H01L2224/05007 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05541 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05666 ,  H01L2224/05684 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/13005 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13144 ,  H01L2924/381 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2224/05647 ,  H01L2924/04941 ,  H01L2924/00012 ,  H01L2924/207

Abstract: Semiconductor device and method for fabricating the same are provided. The semiconductor device comprises a first metal wiring line, a chip pad which is electrically connected with the first metal wiring line and has a first width, a passivation layer which encloses the chip pad and includes a contact hole, a first barrier pattern formed on a side wall of the contact hole and a top surface of the passivation layer, a contact filling the contact hole on the first barrier pattern, and a bump, which is formed of the same material as the contact, has a second width which is smaller than the first width, and is overlaid with the first metal wiring line and the chip pad, the bump being entirely overlapped with the chip pad.

Abstract translation: 提供半导体装置及其制造方法。 半导体器件包括第一金属布线，与第一金属布线电连接并具有第一宽度的芯片焊盘，封装芯片焊盘并包括接触孔的钝化层，形成在第一金属布线 接触孔的侧壁和钝化层的上表面，填充第一阻挡图案上的接触孔的接触部和由与接触件相同的材料形成的凸块具有小于第二宽度的第二宽度 第一宽度，并且与第一金属布线和芯片焊盘重叠，凸块与芯片焊盘完全重叠。

公开(公告)号：US20140035017A1

公开(公告)日：2014-02-06

申请号：US14050744

申请日：2013-10-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Oh-Kyum Kwon ,  Tae-Jung Lee ,  Kyoung-Eun Uhn ,  Byung-Sun Kim

IPC: H01L29/78 ,  H01L29/94

CPC classification number: H01L29/78 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11558 ,  H01L29/94

Abstract: A nonvolatile memory device has a first active region and a second active region defined in a substrate by a device isolation layer, a Metal Oxide Silicon Field-Effect Transistor (MOSFET) disposed on the first active region and including a first electrode pattern, and a Metal Oxide Silicon (MOS) capacitor disposed on the second active region and including a second electrode pattern, and in which the first electrode pattern is narrower in the widthwise direction of the channel of the MOSFET than the first active region.

Abstract translation: 非易失性存储器件具有通过器件隔离层在衬底中限定的第一有源区和第二有源区，设置在第一有源区上并包括第一电极图的金属氧化物半导体场效应晶体管（MOSFET） 金属氧化物硅（MOS）电容器，其设置在第二有源区并且包括第二电极图案，并且其中第一电极图案在MOSFET的沟道的宽度方向上比第一有源区域窄。