公开(公告)号：US20200303512A1

公开(公告)日：2020-09-24

申请号：US16595187

申请日：2019-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YEONKWANG LEE ,  Sungmin Kang ,  Kyungmin Kim ,  Minhee Uh ,  Jun-Gu Kang ,  Youngmok Kim

IPC: H01L29/49 ,  H01L27/092 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/265

Abstract: A semiconductor device includes a substrate, in which a lower semiconductor layer, an insulating gapfill layer, and an upper semiconductor layer are sequentially stacked. A gate structure is disposed on the upper semiconductor layer. A source/drain electrode is disposed on a sidewall of the gate structure. A semiconductor pattern is disposed between the source/drain electrode and the upper semiconductor layer. The gate structure includes a gate electrode and a spacer structure. The spacer structure includes a first spacer pattern, a second spacer pattern, and a third spacer pattern, sequentially disposed on a sidewall of the gate electrode. The semiconductor pattern is extended to a region below a bottom surface of the third spacer pattern and is connected to the second spacer pattern.

公开(公告)号：US10937882B2

公开(公告)日：2021-03-02

申请号：US16595187

申请日：2019-10-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonkwang Lee ,  Sungmin Kang ,  Kyungmin Kim ,  Minhee Uh ,  Jun-Gu Kang ,  Youngmok Kim

IPC: H01L29/06 ,  H01L29/49 ,  H01L27/092 ,  H01L27/12 ,  H01L21/265 ,  H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device includes a substrate, in which a lower semiconductor layer, an insulating gapfill layer, and an upper semiconductor layer are sequentially stacked. A gate structure is disposed on the upper semiconductor layer. A source/drain electrode is disposed on a sidewall of the gate structure. A semiconductor pattern is disposed between the source/drain electrode and the upper semiconductor layer. The gate structure includes a gate electrode and a spacer structure. The spacer structure includes a first spacer pattern, a second spacer pattern, and a third spacer pattern, sequentially disposed on a sidewall of the gate electrode. The semiconductor pattern is extended to a region below a bottom surface of the third spacer pattern and is connected to the second spacer pattern.