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    DELAY LOCKED LOOP INCLUDING A DELAY CODE GENERATOR
    2.
    发明申请
    DELAY LOCKED LOOP INCLUDING A DELAY CODE GENERATOR 审中-公开

    公开(公告)号：US20170338825A1

    公开(公告)日：2017-11-23

    申请号：US15599191

    申请日：2017-05-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hoon Lee ,  Donghun Lee ,  Jaewon Lee

    IPC: H03L7/081 ,  H03L7/091 ,  H03K19/20

    CPC classification number: H03L7/0818 ,  H03K5/131 ,  H03K19/20 ,  H03K2005/00234 ,  H03L7/0816 ,  H03L7/085 ,  H03L7/091 ,  H03L7/10

    Abstract: A delay locked loop includes a delay line, a delay circuit, a phase detector, a delay code generator, and a delay controller. The delay line may delay an input clock signal in units of unit delay in response to a delay control code to generate an output clock signal. The delay circuit may delay the output clock signal to generate a delay clock signal. The phase detector may compare the input clock signal and the delay clock signal to generate a phase detection signal. The delay code generator may compare the input clock signal and the delay clock signal to detect a phase difference therebetween, and generate a delay code using the phase difference. The delay controller may generate the delay control code using the delay code and the phase detection signal.

    Semiconductor device capable of adjusting memory page size based on a row address, a bank address and a power supply voltage
    4.
    发明授权
    Semiconductor device capable of adjusting memory page size based on a row address, a bank address and a power supply voltage 有权
    能够基于行地址，存储体地址和电源电压来调整存储器页面大小的半导体器件

    公开(公告)号：US08804455B2

    公开(公告)日：2014-08-12

    申请号：US13828604

    申请日：2013-03-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hoon Lee ,  Uk Song Kang ,  Hoe Ju Chung

    IPC: G11C8/12

    CPC classification number: G11C8/10 ,  G11C5/00 ,  G11C5/02 ,  G11C8/06 ,  G11C8/12

    Abstract: A semiconductor device includes a memory cell array comprising a plurality of banks and a page size controller. The page size controller decodes a part of a bank selection address or a power supply voltage and a remaining part of the bank selection address to enable one of the plurality of banks or enable two of the plurality of banks to set a page size of the semiconductor device.

    Abstract translation: 半导体器件包括包括多个存储体的存储单元阵列和页面大小控制器。 页面尺寸控制器解码存储体选择地址或电源电压的一部分以及存储体选择地址的剩余部分，以使得多个存储体中的一个存储体使能或使多个存储体中的两个可以设置半导体的页面大小 设备。

    Delay locked loop including a delay code generator
    7.
    发明授权
    Delay locked loop including a delay code generator 有权

    公开(公告)号：US10305494B2

    公开(公告)日：2019-05-28

    申请号：US15599191

    申请日：2017-05-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hoon Lee ,  Donghun Lee ,  Jaewon Lee

    IPC: H03L7/06 ,  H03L7/081 ,  H03L7/091 ,  H03K19/20 ,  H03K5/131 ,  H03K5/00

    Abstract: A delay locked loop includes a delay line, a delay circuit, a phase detector, a delay code generator, and a delay controller. The delay line may delay an input clock signal in units of unit delay in response to a delay control code to generate an output clock signal. The delay circuit may delay the output clock signal to generate a delay clock signal. The phase detector may compare the input clock signal and the delay clock signal to generate a phase detection signal. The delay code generator may compare the input clock signal and the delay clock signal to detect a phase difference therebetween, and generate a delay code using the phase difference. The delay controller may generate the delay control code using the delay code and the phase detection signal.

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