公开(公告)号：US10714149B2

公开(公告)日：2020-07-14

申请号：US16053129

申请日：2018-08-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-hwan Jeon

IPC: G11C5/06 ,  H01L25/10 ,  G06F13/16 ,  G06F3/06 ,  H01L25/18 ,  G11C7/22 ,  G11C5/04 ,  G11C7/10

Abstract: A semiconductor package with clock sharing, which is suitable for an electronic system having low power consumption characteristics, is provided. The semiconductor package includes a lower package including a lower package substrate and a memory controller mounted on the lower package substrate, an upper package stacked on the lower package and including an upper package substrate and a memory device mounted on the upper package substrate, and a plurality of vertical interconnections electrically connecting the lower package to the upper package. The semiconductor package is configured to cause the memory controller to output a first data clock signal used for a channel that is an independent data interface between the memory controller and the memory device, branch the first data clock signal, and provide the branched first data clock signal to the memory device.

公开(公告)号：US10937466B2

公开(公告)日：2021-03-02

申请号：US16880506

申请日：2020-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-hwan Jeon

IPC: G11C5/06 ,  H01L25/10 ,  G06F13/16 ,  G06F3/06 ,  H01L25/18 ,  G11C7/22 ,  G11C5/04 ,  G11C7/10

Abstract: A semiconductor package with clock sharing, which is suitable for an electronic system having low power consumption characteristics, is provided. The semiconductor package includes a lower package including a lower package substrate and a memory controller mounted on the lower package substrate, an upper package stacked on the lower package and including an upper package substrate and a memory device mounted on the upper package substrate, and a plurality of vertical interconnections electrically connecting the lower package to the upper package. The semiconductor package is configured to cause the memory controller to output a first data clock signal used for a channel that is an independent data interface between the memory controller and the memory device, branch the first data clock signal, and provide the branched first data clock signal to the memory device.

公开(公告)号：US09985619B2

公开(公告)日：2018-05-29

申请号：US15206622

申请日：2016-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoon Lee ,  Joung-wook Moon ,  Seong-hwan Jeon

IPC: H03L7/06 ,  H03K5/156 ,  H03L7/089

CPC classification number: H03K5/1565 ,  H03L7/0891

Abstract: A duty cycle corrector (DCC) includes a duty corrector circuit configured to adjust a duty of an input signal to output a duty-adjusted signal; a duty detector circuit configured to generate a correction code associated with the adjustment of the duty, based on a charge pump operation and a counting operation; and a timing controller configured to generate a first control signal associated with the charge pump operation and a second control signal associated with the counting operation in synchronization with a first clock.