公开(公告)号：US09972717B2

公开(公告)日：2018-05-15

申请号：US15228421

申请日：2016-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Jong Jeong ,  Jeong-Yun Lee ,  Geo-Myung Shin ,  Dong-Suk Shin ,  Si-Hyung Lee ,  Seo-Jin Jeong

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/775 ,  H01L29/41 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a gate electrode which extends along a second direction different from the first direction and is formed on the first portion; and a first source/drain region which is formed around the second portion protruding further upward than a top surface of the field insulating layer and contacts the field insulating layer, wherein the second portion is disposed on both sides of the first portion in the first direction and is more recessed than the first portion, a top surface of the first portion and a top surface of the second portion protrude further upward than the top surface of the field insulating layer, and a profile of sidewalls of the second portion is continuous.

公开(公告)号：US09768300B2

公开(公告)日：2017-09-19

申请号：US15406018

申请日：2017-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

公开(公告)号：US09728645B2

公开(公告)日：2017-08-08

申请号：US15146106

申请日：2016-05-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyuk Kim ,  Geo-Myung Shin ,  Dong-Suk Shin

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/02 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of manufacturing a semiconductor device includes partially removing an upper portion of an active fin of a substrate loaded in a chamber to form a trench; and forming a source/drain layer in the trench, which includes providing a silicon source gas, a germanium source gas, an etching gas and a carrier gas into the chamber to perform a selective epitaxial growth (SEG) process using a top surface of the active fin exposed by the trench as a seed so that a silicon-germanium layer is grown; and purging the chamber by providing the carrier gas into the chamber to etch the silicon-germanium layer.

公开(公告)号：US20160343859A1

公开(公告)日：2016-11-24

申请号：US15228421

申请日：2016-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yeong-Jong JEONG ,  Jeong-Yun Lee ,  Geo-Myung Shin ,  Dong-Suk Shin ,  Si-Hyung Lee ,  Seo-Jin Jeong

IPC: H01L29/78 ,  H01L29/161 ,  H01L21/8238 ,  H01L29/165 ,  H01L29/06 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16

CPC classification number: H01L29/7848 ,  B82Y10/00 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/775 ,  H01L29/78 ,  H01L29/7851 ,  H01L29/7853 ,  H01L29/78696

Abstract: A semiconductor device and a method of fabricating the same are provided. The semiconductor device comprises a first multi-channel active pattern which is defined by a field insulating layer, extends along a first direction, and includes a first portion and a second portion; a gate electrode which extends along a second direction different from the first direction and is formed on the first portion; and a first source/drain region which is formed around the second portion protruding further upward than a top surface of the field insulating layer and contacts the field insulating layer, wherein the second portion is disposed on both sides of the first portion in the first direction and is more recessed than the first portion, a top surface of the first portion and a top surface of the second portion protrude further upward than the top surface of the field insulating layer, and a profile of sidewalls of the second portion is continuous.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括由场绝缘层限定的第一多沟道有源图案，沿着第一方向延伸，并且包括第一部分和第二部分; 栅极电极，沿着与第一方向不同的第二方向延伸并形成在第一部分上; 以及第一源极/漏极区域，其围绕所述第二部分形成在所述场绝缘层的顶表面之上并且与所述场绝缘层接触的位置，其中所述第二部分设置在所述第一部分的所述第一方向的两侧 并且比第一部分更凹陷，第一部分的顶表面和第二部分的顶表面比场绝缘层的顶表面进一步向上突出，并且第二部分的侧壁的轮廓是连续的。

公开(公告)号：US20160141381A1

公开(公告)日：2016-05-19

申请号：US14816568

申请日：2015-08-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kook-Tae KIM ,  Ho-Sung Son ,  Geo-Myung Shin ,  Dong-Suk Shin ,  Si-Hyung Lee ,  Ji-Hye Yi ,  Sung-Hoon Jung ,  Yeong-Jong Jeong

IPC: H01L29/423 ,  H01L29/08 ,  H01L29/51 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/7848 ,  H01L29/785

Abstract: Semiconductor devices and methods for fabricating the same are provided. The semiconductor devices include a fin active pattern formed to project from a substrate, a gate electrode formed to cross the fin active pattern on the substrate, a gate spacer formed on a side wall of the gate electrode and having a low dielectric constant and an elevated source/drain formed on both sides of the gate electrode on the fin active pattern. The gate spacer includes first, second and third spacers that sequentially come in contact with each other in a direction in which the gate spacer goes out from the gate electrode, and a carbon concentration of the second spacer is lower than carbon concentrations of the first and third spacers.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括从衬底突出形成的鳍状有源图案，形成为跨越衬底上的鳍状活性图案的栅极电极，形成在栅电极的侧壁上并具有低介电常数和升高的栅极间隔 源极/漏极形成在鳍状物图案上的栅电极的两侧。 栅极间隔物包括在栅极间隔物从栅电极出来的方向上依次相互接触的第一，第二和第三间隔物，第二间隔物的碳浓度低于第一和第二间隔物的碳浓度， 第三间隔物。

公开(公告)号：US09847224B2

公开(公告)日：2017-12-19

申请号：US14519516

申请日：2014-10-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyuk Kim ,  Geo-Myung Shin ,  Dong-Suk Shin

IPC: H01L21/311 ,  H01L29/16 ,  H01L21/02 ,  H01L21/8238 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/165 ,  H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L27/12 ,  H01L27/11

CPC classification number: H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/7848

Abstract: A semiconductor device includes: a substrate including a plurality of first active regions and a plurality of second active regions; a plurality of first gate structures formed above the first active regions, respectively, and a plurality of second gate structures formed above the second active regions, respectively; and a plurality of first source/drain layers corresponding to the first gate structures, respectively, and a plurality of second source/drain layers corresponding to the second gate structures, respectively, wherein a width of each of the first source/drain layers is smaller than a width of each of the second source/drain layers.

公开(公告)号：US09548301B2

公开(公告)日：2017-01-17

申请号：US15009276

申请日：2016-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-Suk Shin ,  Hyun-Chul Kang ,  Dong-Hyun Roh ,  Pan-Kwi Park ,  Geo-Myung Shin ,  Nae-In Lee ,  Chul-Woong Lee ,  Hoi-Sung Chung ,  Young-Tak Kim

IPC: H01L27/088 ,  H01L29/49 ,  H01L29/78 ,  H01L21/8234 ,  H01L27/02 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L29/7848 ,  H01L21/823412 ,  H01L21/823425 ,  H01L27/0207 ,  H01L27/088 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/4966 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7836

Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.

Abstract translation: 提供了包括凹部中的应力器的半导体器件和形成半导体器件的方法。 所述方法可以包括在有源区中形成沟槽，并且沟槽可以包括有源区的切口部分。 所述方法还可以包括在沟槽中形成嵌入的应力源。 嵌入式应力器可以包括下半导体层和上半导体层，其宽度比下半导体层的宽度窄。 上半导体层的一侧可以不与下半导体层的一侧对准，并且上半导体层的最上表面可以高于有源区的最上表面。

公开(公告)号：US09337031B2

公开(公告)日：2016-05-10

申请号：US14516603

申请日：2014-10-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Hyuk Kim ,  Geo-Myung Shin ,  Dong-Suk Shin

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/165

CPC classification number: H01L29/7851 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02587 ,  H01L21/02609 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/02639 ,  H01L21/823431 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: A method of manufacturing a semiconductor device includes partially removing an upper portion of an active fin of a substrate loaded in a chamber to form a trench; and forming a source/drain layer in the trench, which includes providing a silicon source gas, a germanium source gas, an etching gas and a carrier gas into the chamber to perform a selective epitaxial growth (SEG) process using a top surface of the active fin exposed by the trench as a seed so that a silicon-germanium layer is grown; and purging the chamber by providing the carrier gas into the chamber to etch the silicon-germanium layer.

Abstract translation: 一种制造半导体器件的方法包括：部分去除负载在腔室中的衬底的有源鳍片的上部，以形成沟槽; 以及在所述沟槽中形成源极/漏极层，所述源极/漏极层包括提供硅源气体，锗源气体，蚀刻气体和载气，以进入所述腔室中，以使用所述顶部表面进行选择性外延生长（SEG） 活性鳍作为种子由沟槽暴露，使得硅 - 锗层生长; 以及通过将载气提供到所述室中来清洗所述室，以蚀刻所述硅 - 锗层。