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公开(公告)号：US11942163B2
公开(公告)日：2024-03-26
申请号：US17502832
申请日：2021-10-15
发明人： Yoshiyuki Kawashima
IPC分类号： G11C16/28 , G06N3/063 , G11C11/54 , G11C16/04 , G11C16/10 , G11C16/16 , H01L29/423 , H01L29/792
CPC分类号： G11C16/28 , G06N3/063 , G11C11/54 , G11C16/0466 , G11C16/10 , G11C16/16 , H01L29/4234 , H01L29/792
摘要： In a case of achievement of a neural network circuit using a plurality of nonvolatile memory cells, a technique capable of accurately reading information recorded in the plurality of nonvolatile memory cells is provided. A semiconductor device includes: a plurality of nonvolatile memory cells; a plurality of reference-current cells; and a sense amplifier comparing an electric current flowing in each of the plurality of nonvolatile memory cells and an electric current flowing in each of the plurality of reference-current cells. In this case, each cross-sectional structure of the plurality of reference-current cells is the same as each cross-sectional structure of the plurality of nonvolatile memory cells. The writing operation or the erasing operation is also performed to each of the plurality of reference-current memory cells when the writing operation or the erasing operation is performed to each of the plurality of nonvolatile memory cells.
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公开(公告)号：US10818679B2
公开(公告)日：2020-10-27
申请号：US16460476
申请日：2019-07-02
发明人： Digh Hisamoto , Yoshiyuki Kawashima
IPC分类号： H01L27/11521 , H01L21/8234 , H01L27/1158 , H01L27/11565 , H01L27/11568
摘要： In a MONOS memory of the split-gate type formed by a field effect transistor formed on a fin, it is prevented that the rewrite lifetime of the MONOS memory is reduced due to charges being locally transferred into and out of an ONO film in the vicinity of the top of the fin by repeating the write operation and the erase operation. By forming a source region at a position spaced downward from a first upper surface of the fin in a region directly below a memory gate electrode, the current is prevented from flowing concentratedly at the upper end of the fin.
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公开(公告)号：US10312252B2
公开(公告)日：2019-06-04
申请号：US15486741
申请日：2017-04-13
发明人： Yoshiyuki Kawashima
IPC分类号： H01L29/08 , H01L21/28 , H01L27/11568 , H01L21/265 , H01L21/324 , H01L27/11573 , H01L29/423 , H01L29/66 , H01L29/792
摘要： A method of manufacturing a semiconductor device having a memory cell for a split-gate MONOS memory with a halo region, which prevents miswriting in the memory cell and worsening of short channel characteristics. In the method, a first diffusion layer of a drain region and a second diffusion layer of a source region in the memory cell for the MONOS memory are formed in different ion implantation steps. The steps are carried out so that the first diffusion layer has a smaller formation depth than the second diffusion layer. After the formation of the layers, the impurities inside the first and second diffusion layers are diffused by heat treatment to form a first diffusion region and a second diffusion region.
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公开(公告)号：US10002768B2
公开(公告)日：2018-06-19
申请号：US15796621
申请日：2017-10-27
IPC分类号： H01L21/28 , H01L49/02 , H01L27/11573 , H01L27/06 , H01L29/66 , H01L29/792
CPC分类号： H01L29/40117 , H01L27/0629 , H01L27/11573 , H01L28/60 , H01L29/66833 , H01L29/792
摘要： In a semiconductor device, a memory cell is formed of a control gate electrode and a memory gate electrode adjacent to each other, a gate insulating film formed below the control gate electrode and an insulating film formed below the memory gate electrode and having a charge accumulating part therein. Also, in this semiconductor device, a capacitive element is formed of a lower electrode, an upper electrode and a capacitive insulating film formed between the upper electrode and the lower electrode. A thickness of the lower electrode is smaller than a thickness of the control gate electrode.
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公开(公告)号：US09722096B2
公开(公告)日：2017-08-01
申请号：US14872089
申请日：2015-09-30
发明人： Yoshiyuki Kawashima , Shoji Yoshida
IPC分类号： H01L21/336 , H01L29/792 , H01L21/28 , H01L21/30 , H01L21/324 , H01L27/11573 , H01L29/66 , H01L29/51
CPC分类号： H01L29/7923 , H01L21/28176 , H01L21/28282 , H01L21/3003 , H01L21/324 , H01L27/11573 , H01L29/513 , H01L29/665 , H01L29/66545 , H01L29/6659 , H01L29/66833 , H01L29/792
摘要： A semiconductor device including a nonvolatile memory cell and a field effect transistor together is improved in performance. In a method of manufacturing a semiconductor device, a hydrogen-containing insulating film is formed before heat treatment of a semiconductor wafer, the hydrogen-containing insulating film covering a gate electrode and agate insulating film in a region that will have a memory cell therein, and exposing a region that will have therein a MISFET configuring a peripheral circuit. Consequently, hydrogen in the hydrogen-containing insulating film is diffused into an interface between the gate insulating film and the semiconductor substrate, and thereby a defect at the interface is selectively repaired.
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公开(公告)号：US09373630B2
公开(公告)日：2016-06-21
申请号：US14989999
申请日：2016-01-07
IPC分类号： H01L21/8234 , H01L27/115 , H01L27/092
CPC分类号： H01L29/7847 , H01L21/28282 , H01L21/28518 , H01L21/3105 , H01L21/823412 , H01L21/823418 , H01L21/823468 , H01L27/0922 , H01L27/1157 , H01L27/11573 , H01L29/42324 , H01L29/4234 , H01L29/66825 , H01L29/66833
摘要： To improve a semiconductor device having a nonvolatile memory. A first MISFET, a second MISFET, and a memory cell are formed, and a stopper film made of a silicon oxide film is formed thereover. Then, over the stopper film, a stress application film made of a silicon nitride film is formed, and the stress application film over the second MISFET and the memory cell is removed. Thereafter, heat treatment is performed to apply a stress to the first MISFET. Thus, a SMT is not applied to each of elements, but is applied selectively. This can reduce the degree of degradation of the second MISFET due to H (hydrogen) in the silicon nitride film forming the stress application film. This can also reduce the degree of degradation of the characteristics of the memory cell due to the H (hydrogen) in the silicon nitride film forming the stress application film.
摘要翻译： 改善具有非易失性存储器的半导体器件。 形成第一MISFET，第二MISFET和存储单元，并在其上形成由氧化硅膜制成的阻挡膜。 然后，在阻挡膜上形成由氮化硅膜构成的应力施加膜，除去第二MISFET和存储单元上的应力施加膜。 此后，进行热处理以向第一MISFET施加应力。 因此，SMT不应用于每个元件，而是被选择性地应用。 这可以降低由于形成应力施加膜的氮化硅膜中的H（氢）导致的第二MISFET的劣化程度。 这也可以由于形成应力施加膜的氮化硅膜中的H（氢）而降低存储单元的特性的劣化程度。
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公开(公告)号：US09299569B2
公开(公告)日：2016-03-29
申请号：US14801798
申请日：2015-07-16
IPC分类号： H01L27/115 , H01L21/28 , H01L29/40
CPC分类号： H01L21/28282 , H01L21/02164 , H01L21/0217 , H01L27/11563 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L29/401 , H01L29/42344 , H01L29/66833
摘要： The present invention improves the performance of a semiconductor device. In a manufacturing method of a semiconductor device, sacrificial oxide films are formed over the side surface of a control gate electrode formed in a memory cell region, the surface of a cap insulating film formed in the memory cell region, and the surface of the part, which remains in a peripheral circuit region, of an insulating film. The step of forming the sacrificial oxide films includes the steps of: oxidizing the side surface of the control gate electrode by a thermal oxidation method; and oxidizing the surface of the cap insulating film and the surface of the part, which remains in the peripheral circuit region, of the insulating film by an ISSG oxidation method.
摘要翻译： 本发明改进了半导体器件的性能。 在半导体器件的制造方法中，在形成在存储单元区域中的控制栅电极的侧表面上形成牺牲氧化物膜，形成在存储单元区域中的帽绝缘膜的表面和部件的表面 ，其保留在绝缘膜的周边电路区域中。 形成牺牲氧化膜的步骤包括以下步骤：通过热氧化法氧化控制栅电极的侧表面; 并通过ISSG氧化法氧化绝缘膜上的帽绝缘膜的表面和保留在外围电路区域中的部分的表面。
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公开(公告)号：US11276702B2
公开(公告)日：2022-03-15
申请号：US16854399
申请日：2020-04-21
发明人： Yoshiyuki Kawashima
IPC分类号： H01L31/028 , H01L27/088 , H01L27/11556 , H01L27/11582 , G11C5/06 , G11C5/02
摘要： Fins lined up in a Y direction, a control gate electrode and a memory gate electrode each extending in the Y direction so as to straddle the fins, a plurality of first plugs electrically connected with a drain region formed in each of the fins, and a plurality of second plugs electrically connected with a source region formed in each of the fins are formed. Here, a N-th plug of the plurality of first plugs lined up in the Y direction is coupled with each of (2N−1)-th and 2N-th fins in the Y direction. Also, a N-th plug of the plurality of second plugs lined up in the Y direction is coupled with each of 2N-th and (2N+1)-th fins in the Y direction.
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公开(公告)号：US11063055B2
公开(公告)日：2021-07-13
申请号：US16676114
申请日：2019-11-06
发明人： Yoshiyuki Kawashima
IPC分类号： H01L27/11534 , H01L27/11526 , H01L21/3213 , H01L21/311
摘要： A second gate dielectric film material and a memory gate electrode material are formed on a semiconductor substrate. The memory gate electrode material and the second gate dielectric film material formed in a peripheral circuit forming region are removed, and a part of each of the memory gate electrode material and the second gate dielectric film material is left in the memory cell forming region. Thereafter, in a state that the semiconductor substrate in the memory cell forming region is covered with a part of each of the memory gate electrode material and the second gate dielectric film material, heat treatment is performed to the semiconductor substrate to form a third gate dielectric film on the semiconductor substrate located in the peripheral circuit forming region. Thereafter, a memory gate electrode and a second gate dielectric film are formed.
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公开(公告)号：US10978385B2
公开(公告)日：2021-04-13
申请号：US16655606
申请日：2019-10-17
IPC分类号： H01L29/66 , H01L23/522 , H01L27/11517 , H01L21/768 , H01L23/532 , H01L21/762 , H01L49/02 , H01L27/11573 , H01L29/94 , H01L27/12 , H01L27/08 , H01L27/06
摘要： This invention is to improve a performance of a semiconductor device. The semiconductor device includes a semiconductor substrate, a p-type well region formed in the semiconductor substrate, a first insulating layer formed over the p-type well region, a semiconductor layer formed over the first insulating layer, a second insulating layer formed over the semiconductor layer, and a conductor layer formed over the second insulating layer. A first capacitive element is comprised of the semiconductor layer, the second insulating layer, and the conductor layer, while a second capacitive element is comprised of the p-type well region, the first insulating layer, and the semiconductor layer, in which each of the semiconductor substrate and the semiconductor layer includes a single crystal silicon layer.
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