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    Non-volatile semiconductor device and method of fabricating embedded non-volatile semiconductor memory device with sidewall gate
    2.
    发明授权
    Non-volatile semiconductor device and method of fabricating embedded non-volatile semiconductor memory device with sidewall gate 有权
    非易失性半导体器件和制造具有侧壁栅极的嵌入式非易失性半导体存储器件的方法

    公开(公告)号：US08679915B2

    公开(公告)日：2014-03-25

    申请号：US13671482

    申请日：2012-11-07

    Applicant: Renesas Electronics Corporation

    Inventor： Kan Yasui ,  Digh Hisamoto ,  Tetsuya Ishimaru ,  Shin-ichiro Kimura

    IPC: H01L21/00

    CPC classification number: H01L27/115 ,  G11C16/0425 ,  H01L27/11568 ,  H01L29/42344

    Abstract: A method of manufacturing a non-volatile semiconductor memory device is provided which overcomes a problem of penetration of implanted ions due to the difference of an optimal gate height in simultaneous formation of a self-align split gate type memory cell utilizing a side wall structure and a scaled MOS transistor. A select gate electrode to form a side wall in a memory area is formed to be higher than that of the gate electrode in a logic area so that the height of the side wall gate electrode of the self-align split gate memory cell is greater than that of the gate electrode in the logic area. Height reduction for the gate electrode is performed in the logic area before gate electrode formation.

    Abstract translation: 提供了一种制造非易失性半导体存储器件的方法，其克服了由于利用侧壁结构同时形成自对准分裂栅型存储单元而产生的最佳栅极高度的差异而引入的注入离子的问题，以及 一个缩放的MOS晶体管。 形成在存储区域中形成侧壁的选择栅电极比逻辑区域中的栅电极高，使得自对准分离栅极存储单元的侧壁栅电极的高度大于 在逻辑区域的栅电极。 栅极电极的高度降低在栅电极形成之前的逻辑区域中进行。

    SEMICONDUCTOR DEVICE AND METHOD OF DRIVING SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF DRIVING SEMICONDUCTOR DEVICE 有权
    半导体器件和驱动器件的方法

    公开(公告)号：US20160379713A1

    公开(公告)日：2016-12-29

    申请号：US15152391

    申请日：2016-05-11

    Applicant: Renesas Electronics Corporation

    Inventor： Tsuyoshi ARIGANE ,  Daisuke Okada ,  Digh Hisamoto

    IPC: G11C16/04 ,  H01L29/51 ,  H01L27/115 ,  G11C16/14 ,  H01L29/423

    CPC classification number: G11C16/0466 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/344 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/42344 ,  H01L29/511 ,  H01L29/518 ,  H01L29/792

    Abstract: A first potential and a second potential lower than the first potential are applied to a first end of a memory gate electrode part of the nonvolatile memory and to a second end of the memory gate electrode part, respectively, so that a current is caused to flow in a direction in which the memory gate electrode part extends, then, a hole is injected from the memory gate electrode part into a charge accumulating part below it, therefore, an electron accumulated in the charge accumulating part is eliminated. By causing the current to flow through the memory gate electrode part of a memory cell region as described above, Joule heat can be generated to heat the memory cell. Consequently, in the erasing by a FN tunneling method in which the erasing characteristics degrade at a low temperature, the erasing speed can be improved by heating the memory gate electrode part.

    Abstract translation: 低于第一电位的第一电势和第二电位被分别施加到非易失性存储器的存储栅电极部分的第一端和存储栅电极部分的第二端，使得电流流过 在存储栅电极部分延伸的方向上，从存储栅电极部分注入空穴到其下方的电荷累积部分，因此，积累在电荷累积部分中的电子被消除。 通过使电流流过如上所述的存储单元区域的存储栅电极部分，可以产生焦耳热以加热存储单元。 因此，在擦除特性在低温下劣化的FN隧穿法的擦除中，通过加热存储栅电极部分可以提高擦除速度。

    Semiconductor device and method of manufacturing same
    5.
    发明授权
    Semiconductor device and method of manufacturing same 有权
    半导体装置及其制造方法

    公开(公告)号：US09257446B2

    公开(公告)日：2016-02-09

    申请号：US14548595

    申请日：2014-11-20

    Applicant: Renesas Electronics Corporation

    Inventor： Tsuyoshi Arigane ,  Daisuke Okada ,  Digh Hisamoto

    IPC: H01L27/115 ,  H01L29/51 ,  H01L29/423 ,  H01L21/28

    CPC classification number: H01L29/66833 ,  H01L21/2815 ,  H01L21/28158 ,  H01L21/28282 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/42364 ,  H01L29/511 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/792

    Abstract: To provide a semiconductor device having a nonvolatile memory improved in characteristics. In the semiconductor device, a nonvolatile memory has a high-k insulating film (high dielectric constant film) between a control gate electrode portion and a memory gate electrode portion and a transistor of a peripheral circuit region has a high-k/metal configuration. The high-k insulating film arranged between the control gate electrode portion and the memory gate electrode portion relaxes an electric field intensity at the end portion (corner portion) of the memory gate electrode portion on the side of the control gate electrode portion. This results in reduction in uneven distribution of charges in a charge accumulation portion (silicon nitride film) and improvement in erase accuracy.

    Abstract translation: 提供具有改善特性的非易失性存储器的半导体器件。 在半导体器件中，非易失性存储器在控制栅电极部分和存储栅电极部分之间具有高k绝缘膜（高介电常数膜），并且外围电路区域的晶体管具有高k /金属构造。 布置在控制栅电极部分和存储栅电极部分之间的高k绝缘膜松弛在控制栅电极部分一侧的存储栅电极部分的端部（拐角部分）的电场强度。 这导致电荷累积部分（氮化硅膜）中电荷的不均匀分布的减少和擦除精度的提高。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 有权

    公开(公告)号：US11342430B2

    公开(公告)日：2022-05-24

    申请号：US17084097

    申请日：2020-10-29

    Applicant: RENESAS ELECTRONICS CORPORATION

    Inventor： Digh Hisamoto ,  Yoshiyuki Kawashima ,  Takashi Hashimoto

    IPC: H01L29/423 ,  H01L21/28 ,  H01L29/10 ,  H01L29/78 ,  H01L29/792 ,  H01L27/11568

    Abstract: A semiconductor device has a split-gate type MONOS structure using a FinFET, and it includes a source and a drain each formed of an n-type impurity diffusion layer, a first channel forming layer which is formed under a control gate and is formed of a semiconductor layer doped with a p-type impurity, and a second channel forming layer which is formed under a memory gate and is formed of a semiconductor layer doped with an n-type impurity. Further, the semiconductor device includes a p-type semiconductor layer which is formed under the second channel forming layer and has an impurity concentration higher than an impurity concentration of a semiconductor substrate.

    Semiconductor device and method of driving semiconductor device
    8.
    发明授权
    Semiconductor device and method of driving semiconductor device 有权

    公开(公告)号：US09558826B2

    公开(公告)日：2017-01-31

    申请号：US15152391

    申请日：2016-05-11

    Applicant: Renesas Electronics Corporation

    Inventor： Tsuyoshi Arigane ,  Daisuke Okada ,  Digh Hisamoto

    IPC: G11C16/04 ,  G11C16/14 ,  H01L29/423 ,  H01L27/115 ,  H01L29/51 ,  G11C16/34

    Abstract: A first potential and a second potential lower than the first potential are applied to a first end of a memory gate electrode part of the nonvolatile memory and to a second end of the memory gate electrode part, respectively, so that a current is caused to flow in a direction in which the memory gate electrode part extends, then, a hole is injected from the memory gate electrode part into a charge accumulating part below it, therefore, an electron accumulated in the charge accumulating part is eliminated. By causing the current to flow through the memory gate electrode part of a memory cell region as described above, Joule heat can be generated to heat the memory cell. Consequently, in the erasing by a FN tunneling method in which the erasing characteristics degrade at a low temperature, the erasing speed can be improved by heating the memory gate electrode part.

    Semiconductor non-volatile memory device
    10.
    发明授权
    Semiconductor non-volatile memory device 有权
    半导体非易失性存储器件

    公开(公告)号：US09012968B2

    公开(公告)日：2015-04-21

    申请号：US13865374

    申请日：2013-04-18

    Applicant: Renesas Electronics Corporation

    Inventor： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    IPC: H01L29/76 ,  H01L29/423 ,  H01L21/28 ,  H01L27/115 ,  H01L29/792

    CPC classification number: H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

    Abstract: A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

    Abstract translation: 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

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