公开(公告)号：US08816426B2

公开(公告)日：2014-08-26

申请号：US13845005

申请日：2013-03-17

Applicant: Renesas Electronics Corporation

Inventor： Itaru Yanagi ,  Toshiyuki Mine ,  Hirotaka Hamamura ,  Digh Hisamoto ,  Yasuhiro Shimamoto

IPC: H01L29/792

CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/513

Abstract: In a non-volatile memory, writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film, which serves as a charge accumulation layer. The gate electrode of a memory cell has a laminated structure made of a plurality of polysilicon films with different impurity concentrations. In a two-layered structure the gate electrode has a p-type polysilicon film with a low impurity concentration and a p+-type polysilicon film with a high impurity concentration deposited thereon. Holes are injected into the charge accumulation layer from the gate electrode.

Abstract translation: 在非易失性存储器中，通过将电子和空穴注入用作电荷累积层的氮化硅膜中来改变总电荷量来进行写/擦除。 存储单元的栅电极具有由具有不同杂质浓度的多个多晶硅膜制成的叠层结构。 在两层结构中，栅电极具有杂质浓度低的p型多晶硅膜和沉积有高杂质浓度的p +型多晶硅膜。 孔从栅电极注入电荷累积层。

公开(公告)号：US09673339B2

公开(公告)日：2017-06-06

申请号：US14839586

申请日：2015-08-28

Applicant: Renesas Electronics Corporation

Inventor： Itaru Yanagi ,  Toshiyuki Mine ,  Hirotaka Hamamura ,  Digh Hisamoto ,  Yasuhiro Shimamoto

IPC: H01L29/792 ,  H01L29/51 ,  G11C16/04 ,  H01L21/28 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/423

CPC classification number: H01L29/792 ,  G11C16/0466 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11568 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/513

Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p′-type polysilicon film with a high impurity concentration deposited thereon.