公开(公告)号：US10083728B2

公开(公告)日：2018-09-25

申请号：US14324228

申请日：2014-07-06

Applicant: MEDIATEK INC.

Inventor： Yan-Bin Luo ,  Sheng-Ming Chang ,  Bo-Wei Hsieh ,  Ming-Shi Liou ,  Chih-Chien Hung ,  Shang-Pin Chen

IPC: G06F12/00 ,  G11C8/12 ,  G06F13/16

CPC classification number: G11C8/12 ,  G06F12/00 ,  G06F13/1668

Abstract: A memory module, comprising: a first pin, arranged to receive a first signal; a second pin, arranged to receive a second signal; a first conducting path, having a first end coupled to the first pin; at least one memory chip, coupled to the first conducting path for receiving the first signal; a predetermined resistor, having a first terminal coupled to a second end of the first conducting path; and a second conducting path, having a first end coupled to second pin for conducting the second to a second terminal of the predetermined resistor; wherein the first signal and the second are synchronous and configured to be a differential signal, for enabling a selected memory chip from the at least one memory chip to be accessed.

公开(公告)号：US20160143140A1

公开(公告)日：2016-05-19

申请号：US14860718

申请日：2015-09-22

Applicant: Mediatek Inc.

Inventor： Sheng-Ming Chang ,  Chia-Hui Liu ,  Shih-Chieh Lin ,  Chun-Ping Chen

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/115 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0262 ,  H05K1/0298 ,  H05K1/05 ,  H05K1/111 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/095 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A printed circuit board includes a laminated core including at least an internal conductive layer, and a build-up layer on the laminated core. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P. The power/ground ball pad array includes a 4-ball pad unit area that is comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.

Abstract translation: 印刷电路板包括至少包括内部导电层和层压芯上的堆积层的叠层芯。 堆积层包括顶部导电层。 多个微孔设置在积层层中以将顶部导电层与内部导电层电连接。 电源/接地球垫阵列设置在顶部导电层中。 电源/接地球垫阵列包括排列成具有固定球垫间距P的阵列的功率球垫和接地球垫。电源/接地球垫阵列包括仅由一个接地球组成的4球垫单元区域 垫和三个电源球垫，或仅由一个电源球垫和三个地球垫组成。 四球垫单位面积为矩形，尺寸约为2P×2P。

公开(公告)号：US09131602B2

公开(公告)日：2015-09-08

申请号：US13747738

申请日：2013-01-23

Applicant: MediaTek Inc.

Inventor： Sheng-Ming Chang ,  Shih-Chieh Lin ,  Nan-Cheng Chen

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0219 ,  H05K1/0218 ,  H05K1/025 ,  H05K1/0298 ,  H05K1/114 ,  H05K1/115 ,  H05K2201/0723 ,  H05K2201/09672 ,  H05K2201/09709 ,  H05K2201/10522 ,  H05K2201/10674

Abstract: The invention provides a printed circuit board for mobile platforms. An exemplary embodiment of the printed circuit board for mobile platforms includes a core substrate having a first side. A ground plane covers the first side. A first insulating layer covers the ground plane. A plurality of first signal traces and a plurality of first ground traces are alternatively arranged on the first insulating layer. A second insulating layer connects to the first insulating layer. A plurality of second signal traces separated from each other is disposed on the second insulating layer, wherein the second signal traces are disposed directly on spaces between the first signal traces and the first ground traces adjacent thereto.

Abstract translation: 本发明提供一种用于移动平台的印刷电路板。 用于移动平台的印刷电路板的示例性实施例包括具有第一侧的芯基板。 地平面覆盖第一面。 第一绝缘层覆盖接地层。 多个第一信号迹线和多个第一接地迹线交替地布置在第一绝缘层上。 第二绝缘层连接到第一绝缘层。 彼此分离的多个第二信号迹线设置在第二绝缘层上，其中第二信号迹线直接设置在第一信号迹线和与其相邻的第一接地迹线之间的空间上。

公开(公告)号：US20230125573A1

公开(公告)日：2023-04-27

申请号：US18087832

申请日：2022-12-23

Applicant: MEDIATEK INC.

Inventor： Ching-Chih Li ,  Sheng-Ming Chang

IPC: G01R31/28

Abstract: The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.

公开(公告)号：US10194530B2

公开(公告)日：2019-01-29

申请号：US15847852

申请日：2017-12-19

Applicant: MEDIATEK INC.

Inventor： Sheng-Ming Chang ,  Chia-Hui Liu ,  Shih-Chieh Lin ,  Chun-Ping Chen

IPC: H05K1/11 ,  H05K1/02 ,  H01L23/498 ,  H01L23/50 ,  H01L23/00 ,  H05K1/05 ,  H05K1/18

Abstract: A microelectronic system includes a base and a semiconductor package mounted on the base. The base includes an internal conductive layer and a build-up layer on the internal conductive layer. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P, and the power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.

公开(公告)号：US20180116051A1

公开(公告)日：2018-04-26

申请号：US15847852

申请日：2017-12-19

Applicant: MEDIATEK INC.

Inventor： Sheng-Ming Chang ,  Chia-Hui Liu ,  Shih-Chieh Lin ,  Chun-Ping Chen

IPC: H05K1/11 ,  H05K1/02 ,  H01L23/498 ,  H01L23/50 ,  H01L23/00 ,  H05K1/05 ,  H05K1/18

CPC classification number: H05K1/115 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0262 ,  H05K1/0298 ,  H05K1/05 ,  H05K1/111 ,  H05K1/114 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/095 ,  H05K2201/09509 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A microelectronic system includes a base and a semiconductor package mounted on the base. The base includes an internal conductive layer and a build-up layer on the internal conductive layer. The build-up layer includes a top conductive layer. A plurality of microvias is disposed in the build-up layer to electrically connect the top conductive layer with the internal conductive layer. A power/ground ball pad array is disposed in the top conductive layer. The power/ground ball pad array includes power ball pads and ground ball pads arranged in an array with a fixed ball pad pitch P, and the power/ground ball pad array includes a 4-ball pad unit area comprised of only one ground ball pad and three power ball pads, or comprised of only one power ball pad and three ground ball pads. The 4-ball pad unit area has a rectangular shape and a dimension of about 2P×2P.

公开(公告)号：US20200326368A1

公开(公告)日：2020-10-15

申请号：US16828925

申请日：2020-03-24

Applicant: MEDIATEK INC.

Inventor： Ching-Chih Li ,  Sheng-Ming Chang

IPC: G01R31/28

Abstract: The present invention provides a device for testing a chip, wherein the device includes a testing board and an interposer. The testing board has a plurality of pads for providing a plurality of test signals. The interposer board includes a plurality of passive components, and at least one of the passive components is coupled between a supply voltage and a ground voltage, and the supply voltage and the ground voltage are received from a power pad and a ground pad of the plurality of pads of the testing board, respectively; wherein the chip is positioned in the device, the chip receives the test signals including the supply voltage and the ground voltage from the power pad and the ground pad of the testing board, respectively.

公开(公告)号：US10079192B2

公开(公告)日：2018-09-18

申请号：US15064545

申请日：2016-03-08

Applicant: MEDIATEK INC.

Inventor： Ching-Wen Hsiao ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Tung-Hsien Hsieh ,  Sheng-Ming Chang

IPC: H01L23/367 ,  H01L23/50 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L25/16 ,  H01L23/31 ,  H01L23/498 ,  H01L25/065

CPC classification number: H01L23/3675 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/00 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls on respective said solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the package substrate; a first solder connecting the first terminal with the first dummy pad and the chip package; and a second solder connecting the second terminal with the second dummy pad and the chip package.

公开(公告)号：US20170206937A1

公开(公告)日：2017-07-20

申请号：US15297170

申请日：2016-10-19

Applicant: MEDIATEK INC.

Inventor： Sheng-Ming Chang ,  Chun-Wei Chang

IPC: G11C5/04 ,  H01L23/00 ,  H01L25/10 ,  G06F13/42 ,  H01L23/31 ,  G11C14/00 ,  G11C5/06 ,  G06F13/40 ,  H01L23/538 ,  H01L25/065

CPC classification number: G11C5/04 ,  G06F13/4022 ,  G06F13/4282 ,  G06F15/7807 ,  G11C5/06 ,  G11C14/0018 ,  H01L23/3128 ,  H01L23/5386 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2924/15311 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/10537 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151 ,  Y02P70/611 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A hybrid system includes a printed circuit board (PCB) having a main surface, a package-on-package (PoP) having a bottom package mounted on the main surface of the PCB and a top package stacked on the bottom package, and a multi-chip package (MCP) on the main surface of the PCB. The bottom package includes a system-on-chip (SoC) and the top package includes at least one on-package dynamic random access memory (DRAM) die accessible to the SoC. The MCP includes at least one on-board DRAM die accessible to the SoC via a PCB trace.

公开(公告)号：US20160329262A1

公开(公告)日：2016-11-10

申请号：US15064545

申请日：2016-03-08

Applicant: MEDIATEK INC.

Inventor： Ching-Wen Hsiao ,  Tzu-Hung Lin ,  I-Hsuan Peng ,  Tung-Hsien Hsieh ,  Sheng-Ming Chang

IPC: H01L23/367 ,  H01L23/498 ,  H01L25/16 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/3675 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/19 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/02373 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16265 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/92125 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06524 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/19104 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A semiconductor chip package assembly includes a package substrate having a chip mounting surface; a plurality of solder pads disposed on the chip mounting surface; a first dummy pad and a second dummy pad spaced apart from the first dummy pad disposed on the chip mounting surface; a solder mask on the chip mounting surface and partially covering the solder pads, the first dummy pad, and the second dummy pad; a chip package mounted on the chip mounting surface and electrically connected to the package substrate through a plurality of solder balls on respective said solder pads; a discrete device having a first terminal and a second terminal disposed between the chip package and the package substrate; a first solder connecting the first terminal with the first dummy pad and the chip package; and a second solder connecting the second terminal with the second dummy pad and the chip package.

Abstract translation: 半导体芯片封装组件包括具有芯片安装表面的封装衬底; 设置在芯片安装表面上的多个焊盘; 第一虚拟焊盘和与设置在芯片安装表面上的第一虚设焊盘间隔开的第二虚拟焊盘; 在芯片安装表面上的焊接掩模，并且部分地覆盖焊盘，第一虚拟焊盘和第二虚拟焊盘; 芯片封装，其安装在芯片安装表面上，并通过相应的所述焊盘上的多个焊球电连接到封装基板; 分立器件，其具有设置在所述芯片封装和所述封装衬底之间的第一端子和第二端子; 将所述第一端子与所述第一虚拟焊盘和所述芯片封装相连接的第一焊料; 以及将第二端子与第二虚拟焊盘和芯片封装件连接的第二焊料。