公开(公告)号：US10109341B2

公开(公告)日：2018-10-23

申请号：US15298262

申请日：2016-10-20

Applicant: MEDIATEK Inc.

Inventor： Bo-Wei Hsieh ,  Shang-Pin Chen

IPC: G11C7/00 ,  G11C11/4074 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4072

Abstract: A memory controller is connected with a memory. The memory controller includes a clock signal pin and plural command pins. The clock signal pin is connected with the memory for transmitting a clock signal to the memory. The plural command pins are connected with the memory for transmitting a command signal to the memory. The command signal contains an entering self-refresh command and an entering power down command. The memory enters a self-refresh state when the entering self-refresh command is executed. The memory enters a power down state when the entering power down command is executed.

公开(公告)号：US20210295894A1

公开(公告)日：2021-09-23

申请号：US17238000

申请日：2021-04-22

Applicant: MediaTek Inc.

Inventor： Bo-Wei Hsieh ,  Ching-Yeh Hsuan ,  Shang-Pin Chen

IPC: G11C11/4076 ,  G11C11/4093 ,  G11C11/408 ,  G11C7/10

Abstract: A training method for a memory system is provided. The memory system includes a memory controller and a memory. The memory controller is connected with the memory. The training method includes the following steps. Firstly, the memory samples n command/address signals according to a first signal edge and a second signal edge of a clock signal to acquire a first sampled content and a second sampled content. The memory selectively outputting one of the first sampled content and the second sampled content through m data signals to the memory controller in response to a control signal. Moreover, m is larger than n and smaller than 2n.

公开(公告)号：US20180374533A1

公开(公告)日：2018-12-27

申请号：US16011779

申请日：2018-06-19

Applicant: MEDIATEK INC.

Inventor： Der-Ping Liu ,  Bo-Wei Hsieh

IPC: G11C11/406 ,  G11C11/4076 ,  G11C7/22

Abstract: A refresh control method for a memory controller of a memory system is provided. The memory controller is connected with a memory. The memory includes plural memory banks. The refresh control method includes the following steps. Firstly, a refresh state of the memory device is read, and thus a refresh window is realized. Then, a refresh command is issued to the memory device according to the refresh state. The refresh command contains a memory bank number field and a memory bank count field. The memory bank count field indicates a first count. The first count of memory banks are selected from the plural memory banks of the memory device according to the memory bank number field and the first count. Moreover, a refresh operation is performed on the first count of memory banks.

公开(公告)号：US10163485B2

公开(公告)日：2018-12-25

申请号：US15480382

申请日：2017-04-06

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Bo-Wei Hsieh

IPC: G11C11/4076 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/4096 ,  G06F13/16 ,  G11C29/02

Abstract: A memory module includes a memory interface circuit and a training signal generator. The memory interface circuit includes a plurality of terminals for communicating with a memory controller, and the terminals comprise at least a plurality of data terminals. The training signal generator is coupled to the memory interface circuit, and is arranged for generating a training signal to the memory controller through only a portion of the data terminals or a specific terminal instead of the data terminals when the memory module receives a training request from the memory controller.

公开(公告)号：US09829914B2

公开(公告)日：2017-11-28

申请号：US15424891

申请日：2017-02-06

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Bo-Wei Hsieh

IPC: G06F1/12 ,  G06F1/08

CPC classification number: G06F1/12 ,  G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1093 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/0994 ,  H03L2207/50

Abstract: A method for performing signal control of an electronic device and an associated apparatus are provided, where the method includes the steps of: when it is detected that a phase difference between a data signal and a clock signal reaches a predetermined value, controlling the clock signal to switch from a first frequency to a second frequency, wherein both of the clock signal and the data signal are signals of the electronic device (e.g. signals of a memory interface circuit of the electronic device); applying at least one phase shift to the data signal until a condition is satisfied; and controlling the clock signal to switch from the second frequency to the first frequency; wherein the data signal is calibrated with respect to the clock signal with aid of the at least one phase shift.

公开(公告)号：US09812187B2

公开(公告)日：2017-11-07

申请号：US15424882

申请日：2017-02-05

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Bo-Wei Hsieh

IPC: G11C11/40 ,  G11C11/4076 ,  G11C11/4093 ,  G11C5/06 ,  G11C7/22

CPC classification number: G11C11/4076 ,  G06F13/4086 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  G11C11/4093 ,  G11C2207/105 ,  H03K19/0005 ,  H04L25/0298

Abstract: A memory system includes a memory controller and a memory module. The memory controller is arranged for selectively generating at least a clock signal and an inverted clock signal. The memory module includes a first termination resistor, a second termination resistor and a switch module, where a first node of the first termination resistor is to receive the clock signal, a second termination resistor, wherein a first node of the second termination resistor is to receive the inverted clock signal, and the switch module is arranged for selectively connecting or disconnecting a second node of the second termination resistor to a second node of the first termination resistor.

公开(公告)号：US10008255B2

公开(公告)日：2018-06-26

申请号：US15702845

申请日：2017-09-13

Applicant: MediaTek Inc.

Inventor： Bo-Wei Hsieh

IPC: G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/419

CPC classification number: G11C11/4076 ,  G11C7/109 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4087 ,  G11C11/4096 ,  G11C11/419 ,  G11C2207/2281 ,  G11C2207/229

Abstract: An operating method for a dynamic random access memory (DRAM) obtains a plurality of first sub-commands of a first activate command via a command bus, and obtaining a plurality of first address information regarding a plurality of first portions of a first row address of a specific bank via an address bus. Each of the first sub-commands corresponds to an individual first portion of the first row address of the specific bank. The method further combines the first portions of the first row address of the specific bank in response to a specific sub-command of the first sub-commands, so as to obtain a first complete row address; and obtains an access command via the command bus.

公开(公告)号：US09871518B2

公开(公告)日：2018-01-16

申请号：US15247903

申请日：2016-08-25

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Chia-Yu Chan ,  Bo-Wei Hsieh

IPC: H03K19/00 ,  G11C5/00 ,  G11C7/10 ,  G11C11/4074 ,  G06F3/06 ,  H03K19/0175 ,  H03K19/018 ,  H03K19/0185 ,  G11C5/04

CPC classification number: H03K19/0005 ,  G06F3/0625 ,  G06F3/0659 ,  G06F3/0683 ,  G11C5/04 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4074 ,  H03K19/017545 ,  H03K19/01825 ,  H03K19/018557

Abstract: A memory interface circuit includes a first variable impedance circuit coupled between a first supply voltage and a pad, and a second variable impedance circuit coupled between a second supply voltage and the pad; wherein when the first supply voltage changes, at least one of the first variable impedance circuit and the second variable impedance circuit is controlled to have different setting in response to the changing of the first supply voltage.

公开(公告)号：US20170345480A1

公开(公告)日：2017-11-30

申请号：US15480382

申请日：2017-04-06

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Bo-Wei Hsieh

IPC: G11C11/4076 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/4096

CPC classification number: G11C11/4076 ,  G06F13/1689 ,  G11C11/406 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/022 ,  Y02D10/14

Abstract: A memory module includes a memory interface circuit and a training signal generator. The memory interface circuit includes a plurality of terminals for communicating with a memory controller, and the terminals comprise at least a plurality of data terminals. The training signal generator is coupled to the memory interface circuit, and is arranged for generating a training signal to the memory controller through only a portion of the data terminals or a specific terminal instead of the data terminals when the memory module receives a training request from the memory controller.

公开(公告)号：US09824728B2

公开(公告)日：2017-11-21

申请号：US14294094

申请日：2014-06-02

Applicant: MEDIATEK INC.

Inventor： Shang-Pin Chen ,  Bo-Wei Hsieh

IPC: H03K17/16 ,  G11C7/10 ,  G11C29/02 ,  G11C5/06 ,  H03K19/0185 ,  H04L25/02 ,  G06F13/16

CPC classification number: G11C7/109 ,  G06F13/1689 ,  G11C5/063 ,  G11C7/1057 ,  G11C7/1084 ,  G11C29/022 ,  G11C29/028 ,  H03K19/018557 ,  H04L25/0278 ,  H04L25/0298

Abstract: A method for performing memory interface calibration in an electronic device, an associated apparatus, and an associated memory controller are provided, where the method includes: controlling a signal on a digital terminal of the memory controller to switch between a plurality of levels, wherein the digital terminal is coupled to a memory of the electronic device; and based on at least one detection result obtained from detecting the signal, calibrating a logical state of the signal to correspond to a level of the plurality of levels. More particularly, the memory controller may include a plurality of command terminals, a plurality of data terminals, and at least one clock terminal, which are used for coupling the memory controller to the memory. For example, the digital terminal may be a command terminal or a data terminal.