公开(公告)号：US11145674B1

公开(公告)日：2021-10-12

申请号：US16841700

申请日：2020-04-07

Applicant: MACRONIX International Co., Ltd.

Inventor： Wei-Liang Lin ,  Wen-Jer Tsai

IPC: H01L27/11582 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/265 ,  H01L27/11568 ,  H01L21/28 ,  H01L21/02

Abstract: A 3D memory device includes a substrate, stacked structures formed on the substrate, common source line (CSL) contacts, and NOR flash memories. The substrate has CSLs and memory cell regions alternately arranged along one direction in parallel. The stacked structures are located on the memory cell regions and include a ground select line (GSL) layer and a word line (WL) layer. The CSL contacts are disposed along another direction to connect the CSLs. The NOR flash memories are disposed in the memory cell regions, and each of the NOR flash memories includes at least an epitaxial pillar through the stacked structure, a charge-trapping layer located between the epitaxial pillar and the WL layer, and a high-k layer located between the charge-trapping layer and the WL layer. The epitaxial pillar has a retracted sidewall at a position passing through the GSL layer.

公开(公告)号：US20210313342A1

公开(公告)日：2021-10-07

申请号：US16841700

申请日：2020-04-07

Applicant: MACRONIX International Co., Ltd.

Inventor： WEI-LIANG LIN ,  Wen-Jer Tsai

IPC: H01L27/11582 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/28 ,  H01L27/11568 ,  H01L21/02 ,  H01L21/265

Abstract: A 3D memory device includes a substrate, stacked structures formed on the substrate, common source line (CSL) contacts, and NOR flash memories. The substrate has CSLs and memory cell regions alternately arranged along one direction in parallel. The stacked structures are located on the memory cell regions and include a ground select line (GSL) layer and a word line (WL) layer. The CSL contacts are disposed along another direction to connect the CSLs. The NOR flash memories are disposed in the memory cell regions, and each of the NOR flash memories includes at least an epitaxial pillar through the stacked structure, a charge-trapping layer located between the epitaxial pillar and the WL layer, and a high-k layer located between the charge-trapping layer and the WL layer. The epitaxial pillar has a retracted sidewall at a position passing through the GSL layer.

公开(公告)号：US11018154B2

公开(公告)日：2021-05-25

申请号：US16543688

申请日：2019-08-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Chang Lu ,  Wen-Jer Tsai ,  Guan-Wei Wu ,  Yao-Wen Chang

IPC: H01L27/11582 ,  H01L29/36 ,  H01L29/10 ,  H01L23/528 ,  H01L21/265 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51

Abstract: A memory device includes a conductive strip stack structure having conductive strips and insulating layers stacked in a staggered manner and a channel opening passing through the conductive strips and the insulating layer; a memory layer disposed in the channel opening and overlying the conductive strips; a channel layer overlying the memory layer; a semiconductor pad extending upwards from a bottom of the channel opening beyond an upper surface of a bottom conductive strip, in contact with the channel layer, and electrically isolated from the conductive strips; wherein the channel layer includes a first portion having a first doping concentration and a second portion having a second doping concentration disposed on the first portion.

公开(公告)号：US20210005241A1

公开(公告)日：2021-01-07

申请号：US16503631

申请日：2019-07-05

Applicant: MACRONIX International Co., Ltd.

Inventor： Chun-Chang Lu ,  Wen-Jer Tsai

IPC: G11C11/4074 ,  G11C11/4097 ,  G11C11/4094 ,  G06F13/16

Abstract: A memory device is provided. The memory device includes a plurality of memory cell blocks and a source voltage generator. Each of the memory cell blocks has at least one memory cell. The source voltage generator is coupled to the plurality of memory cell blocks and configured to cause a source voltage of the memory cell block to be a first voltage according to that a memory cell in each of the memory cell blocks is in a selected state and cause a source voltage of the memory cell block to be a second voltage according to that all memory cells in each of the memory cell blocks are in an unselected state, wherein an absolute value of the first voltage is less than an absolute value of the second voltage. In addition, an operating method of the memory device is also provided.

公开(公告)号：US10340017B2

公开(公告)日：2019-07-02

申请号：US15803986

申请日：2017-11-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Yu-Hung Huang ,  Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Atsuhiro Suzuki ,  Wen-Jer Tsai

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/16 ,  G11C8/14

Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.

公开(公告)号：US09324431B1

公开(公告)日：2016-04-26

申请号：US14606647

申请日：2015-01-27

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Hsien Cheng ,  Wen-Jer Tsai

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/14

CPC classification number: G11C16/0466 ,  G11C16/0408 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/792

Abstract: A nonvolatile memory cell has a semiconductor substrate, a multilayer stack including a charge trapping layer over a floating gate, a top conductive layer, and circuitry controlling program and erase operations on the nonvolatile memory cell. The program and erase operations change a first charge density on the floating gate by a larger magnitude than a second charge density on the charge trapping dielectric layer.

Abstract translation: 非易失性存储单元具有半导体衬底，包括浮置栅极上的电荷俘获层的多层堆叠，顶部导电层以及控制对非易失性存储单元的编程和擦除操作的电路。 编程和擦除操作使浮置栅极上的第一电荷密度比电荷俘获电介质层上的第二电荷密度更大。

公开(公告)号：US20150325584A1

公开(公告)日：2015-11-12

申请号：US14275559

申请日：2014-05-12

Applicant: MACRONIX International Co., Ltd.

Inventor： Chih-Chieh Cheng ,  Shih-Guei Yan ,  Wen-Jer Tsai

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/792

CPC classification number: H01L27/11568 ,  H01L21/762 ,  H01L21/76224 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923

Abstract: Provided is a memory cell including a substrate, two doped regions of a first conductivity type, one doped region of a second conductivity type, two stacked structures, and a first isolation structure. The doped regions of the first conductivity type are respectively disposed in the substrate. The doped region of the second conductivity type is disposed in the substrate between the two doped regions of the first conductivity type. The stacked structures are disposed on the substrate and respectively cover the corresponding doped regions of the first conductivity type and a portion of the doped region of the second conductivity type. Each of the stacked structures includes one charge storage layer. The first isolation structure completely covers and is in contact with the bottom surface of each of the doped regions of the first conductivity type and the bottom surface of the doped region of the second conductivity type.

Abstract translation: 提供了一种存储单元，其包括基板，第一导电类型的两个掺杂区域，第二导电类型的一个掺杂区域，两个堆叠结构和第一隔离结构。 第一导电类型的掺杂区域分别设置在基板中。 第二导电类型的掺杂区域设置在第一导电类型的两个掺杂区域之间的衬底中。 层叠结构设置在基板上并分别覆盖第一导电类型的对应掺杂区域和第二导电类型的掺杂区域的一部分。 每个堆叠结构包括一个电荷存储层。 第一隔离结构完全覆盖并与第一导电类型的每个掺杂区域的底表面和第二导电类型的掺杂区域的底表面接触。

公开(公告)号：US09018085B2

公开(公告)日：2015-04-28

申请号：US14198320

申请日：2014-03-05

Applicant: MACRONIX International Co., Ltd.

Inventor： Shih-Guei Yan ,  Wen-Jer Tsai ,  Cheng-Hsien Cheng

IPC: H01L29/66 ,  H01L21/28 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792 ,  H01L27/115

CPC classification number: H01L29/66833 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating a memory device of this invention includes at least the following steps. A tunnel dielectric layer is formed over a substrate. A gate is fowled over the tunnel dielectric layer. At least one charge storage layer is formed between the gate and the tunnel dielectric layer. Two doped regions are formed in the substrate beside the gate. A word line is formed on and electrically connected to the gate, wherein the word line having a thickness greater than a thickness of the gate.

Abstract translation: 本发明的存储器件的制造方法至少包括以下步骤。 在衬底上形成隧道介电层。 在隧道电介质层上徘徊一扇门。 在栅极和隧道介电层之间形成至少一个电荷存储层。 在栅极旁边的衬底中形成两个掺杂区域。 字线形成在栅极上并电连接到栅极，其中字线的厚度大于栅极的厚度。

公开(公告)号：US20250014671A1

公开(公告)日：2025-01-09

申请号：US18403726

申请日：2024-01-04

Applicant: MACRONIX International Co., Ltd.

Inventor： You-Liang Chou ,  Wen-Jer Tsai

IPC: G11C29/52 ,  G11C16/24 ,  G11C16/26

Abstract: A memory device and a read method therefor are disclosed. The memory device includes first to third memory cell strings. The memory device is a three-dimensional NAND flash memory with high capacity and high performance. Each of the memory cell strings includes first to third memory cells. The read method includes: performing a first read operation of the memory device to the second memory cell in the second memory cell string, the first read operation includes applying a first bit line voltage to a first bit line, a second bit line, and a third bit line; in response to the failure of the first read operation, performing a second read operation of the memory device, the second read operation includes: applying a set of second bit line voltages to the first bit line, the second bit line and the third bit line.

公开(公告)号：US11062759B1

公开(公告)日：2021-07-13

申请号：US16837041

申请日：2020-04-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Cheng-Hsien Cheng ,  Atsuhiro Suzuki ,  Yu-Hung Huang ,  Sheng-Kai Chen ,  Wen-Jer Tsai

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/56 ,  G11C11/409 ,  G11C11/4076

Abstract: A memory device and a programming method thereof are provided. The memory device includes a memory array, a plurality of word lines and a voltage generator. During a programming procedure, one of the word lines is at a selected state and others of the word lines are at a deselected state. Some of the word lines, which are at the deselected state, are classified into a first group and a second group. The first group and the second group are respectively located at two sides of the word line, which is at the selected state. The voltage generator provides a programming voltage to the word line, which is at the select state, during a programming duration. The voltage generator provides a first two-stage voltage waveform to the word lines in the first group and provides a second two-stage voltage waveform to the word lines in the second group.