公开(公告)号：US11145674B1

公开(公告)日：2021-10-12

申请号：US16841700

申请日：2020-04-07

Applicant: MACRONIX International Co., Ltd.

Inventor： Wei-Liang Lin ,  Wen-Jer Tsai

IPC: H01L27/11582 ,  H01L27/11521 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/265 ,  H01L27/11568 ,  H01L21/28 ,  H01L21/02

Abstract: A 3D memory device includes a substrate, stacked structures formed on the substrate, common source line (CSL) contacts, and NOR flash memories. The substrate has CSLs and memory cell regions alternately arranged along one direction in parallel. The stacked structures are located on the memory cell regions and include a ground select line (GSL) layer and a word line (WL) layer. The CSL contacts are disposed along another direction to connect the CSLs. The NOR flash memories are disposed in the memory cell regions, and each of the NOR flash memories includes at least an epitaxial pillar through the stacked structure, a charge-trapping layer located between the epitaxial pillar and the WL layer, and a high-k layer located between the charge-trapping layer and the WL layer. The epitaxial pillar has a retracted sidewall at a position passing through the GSL layer.

公开(公告)号：US11289502B2

公开(公告)日：2022-03-29

申请号：US16727009

申请日：2019-12-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Liang Lin ,  Wen-Jer Tsai

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L21/762 ,  H01L27/11519 ,  H01L27/11565 ,  H01L29/788 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  H01L21/3205 ,  H01L21/3213

Abstract: A memory device includes a substrate having an upper surface; a stacked structure disposed on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer; a second conductive layer and a third insulating layer sequentially stacked on the substrate; a plurality of channel structures penetrating the stacked structure and electrically connected to the substrate, wherein each of the channel structures includes an upper portion corresponding to the second conductive layer and a lower portion corresponding to the first conductive layer; a memory layer disposed between the second conductive layer and the upper portion; and a plurality of isolation structures penetrating the stacked structure to separate the stacked structure into a plurality of sub-stacks.

公开(公告)号：US10741262B2

公开(公告)日：2020-08-11

申请号：US16212551

申请日：2018-12-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Liang Lin ,  Chun-Chang Lu ,  Wen-Jer Tsai ,  Guan-Wei Wu ,  Yao-Wen Chang

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C8/08 ,  H01L27/11556 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11524

Abstract: A programming operation for high density memory, like 3D NAND flash memory, modifies the waveforms applied during program operations to mitigate unwanted disturbance of memory cells not selected for programming during the operation. Generally, the method provides for applying a bias arrangement during an interval of time between program verify pass voltages and program pass voltages in a program sequence that can include a soft ramp down, and pre-turn-on voltages designed to reduce variations in the potential distribution on floating channels of unselected NAND strings during a program operation.

公开(公告)号：US09830992B1

公开(公告)日：2017-11-28

申请号：US15362052

申请日：2016-11-28

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wen-Jer Tsai ,  Wei-Liang Lin ,  Chih-Chieh Cheng

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56 ,  G11C16/14

CPC classification number: G11C16/26 ,  G11C11/5671 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/14 ,  G11C16/3445 ,  G11C16/3459

Abstract: An operation method of a memory cell includes steps of applying a pre pulse before a read pulse is applied, wherein the pre pulse is larger than a maximum threshold voltage or less than a lowest threshold voltage.

公开(公告)号：US12046293B2

公开(公告)日：2024-07-23

申请号：US17820906

申请日：2022-08-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chun-Chang Lu ,  Wen-Jer Tsai ,  Wei-Liang Lin

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/344

Abstract: A memory device and a method for operating selective erase scheme are provided. In an erase operation, a switch voltage is applied to at least one of a string select line or a ground select line of a selected sub-block of a selected block, a gate control voltage is applied to selected word lines of the selected sub-block, and an erase voltage is applied to bit lines and a common source line of the selected sub-block. The switch voltage is smaller than the erase voltage. The gate control voltage is smaller than the switch voltage and the erase voltage.

公开(公告)号：US11641744B2

公开(公告)日：2023-05-02

申请号：US17670570

申请日：2022-02-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Wei-Liang Lin ,  Wen-Jer Tsai

IPC: H10B43/27 ,  H01L21/762 ,  H01L29/423 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L29/788 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  G11C16/04 ,  H01L21/3205 ,  H01L21/3213

Abstract: A memory device and a method for fabricating the memory device are provided. The memory device includes a substrate having an upper surface; a stacked structure disposed on the upper surface of the substrate, wherein the stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer and a third insulating layer sequentially stacked on the substrate; a plurality of channel structures penetrating the stacked structure and electrically connected to the substrate, wherein each of the channel structures includes an upper portion corresponding to the second conductive layer and a lower portion corresponding to the first conductive layer; a memory layer disposed between the second conductive layer and the upper portion; and a plurality of isolation structures penetrating the stacked structure to separate the stacked structure into a plurality of sub-stacks.