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公开(公告)号：US11177000B2
公开(公告)日：2021-11-16
申请号：US16445362
申请日：2019-06-19
发明人： Guan-Wei Wu , Yao-Wen Chang , Chih-Chieh Cheng , I-Chen Yang
摘要： An operating method of a non-volatile memory includes: generating a first programming pulse with a first time period to a target memory cell in a memory array; reading and verifying whether a threshold voltage of the target memory cell reaches a target voltage level; and generating a second programming pulse with a second time period to the target memory cell when the threshold voltage of the target memory cell does not reach the target voltage level, wherein the second time period is longer than the first time period.
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公开(公告)号：US20150325584A1
公开(公告)日：2015-11-12
申请号：US14275559
申请日：2014-05-12
发明人： Chih-Chieh Cheng , Shih-Guei Yan , Wen-Jer Tsai
IPC分类号： H01L27/115 , H01L29/66 , H01L29/792
CPC分类号： H01L27/11568 , H01L21/762 , H01L21/76224 , H01L29/66833 , H01L29/792 , H01L29/7923
摘要： Provided is a memory cell including a substrate, two doped regions of a first conductivity type, one doped region of a second conductivity type, two stacked structures, and a first isolation structure. The doped regions of the first conductivity type are respectively disposed in the substrate. The doped region of the second conductivity type is disposed in the substrate between the two doped regions of the first conductivity type. The stacked structures are disposed on the substrate and respectively cover the corresponding doped regions of the first conductivity type and a portion of the doped region of the second conductivity type. Each of the stacked structures includes one charge storage layer. The first isolation structure completely covers and is in contact with the bottom surface of each of the doped regions of the first conductivity type and the bottom surface of the doped region of the second conductivity type.
摘要翻译： 提供了一种存储单元，其包括基板，第一导电类型的两个掺杂区域，第二导电类型的一个掺杂区域，两个堆叠结构和第一隔离结构。 第一导电类型的掺杂区域分别设置在基板中。 第二导电类型的掺杂区域设置在第一导电类型的两个掺杂区域之间的衬底中。 层叠结构设置在基板上并分别覆盖第一导电类型的对应掺杂区域和第二导电类型的掺杂区域的一部分。 每个堆叠结构包括一个电荷存储层。 第一隔离结构完全覆盖并与第一导电类型的每个掺杂区域的底表面和第二导电类型的掺杂区域的底表面接触。
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公开(公告)号：US09070588B2
公开(公告)日：2015-06-30
申请号：US14459050
申请日：2014-08-13
发明人： Chih-Chieh Cheng , Shih-Guei Yan , Wen-Jer Tsai
IPC分类号： H01L29/792 , H01L27/115 , H01L29/66 , H01L21/28 , H01L29/423
CPC分类号： H01L27/11563 , H01L21/28282 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： A non-volatile memory structure, including a substrate, a plurality of stacked structures, a plurality of first conductive type doped regions, at least one second conductive type doped region, a conductive layer, and a first dielectric layer, is provided. The stacked structures are disposed on the substrate, and each of the stacked structures includes a charge storage structure. The first conductive type doped regions are disposed in the substrate under the corresponding charge storage structures respectively. The second conductive type doped region is disposed in the substrate between the adjacent charge storage structures and has an overlap region with each of the charge storage structures. The conductive layer covers the second conductive type doped region. The first dielectric layer is disposed between the conductive layer and the second conductive type doped region.
摘要翻译： 提供了包括基板，多个堆叠结构，多个第一导电型掺杂区域，至少一个第二导电型掺杂区域，导电层和第一介电层的非易失性存储器结构。 堆叠结构设置在基板上，并且每个堆叠结构都包括电荷存储结构。 第一导电型掺杂区域分别设置在相应的电荷存储结构下的衬底中。 第二导电型掺杂区域设置在相邻的电荷存储结构之间的衬底中，并且与每个电荷存储结构具有重叠区域。 导电层覆盖第二导电型掺杂区域。 第一介电层设置在导电层和第二导电型掺杂区之间。
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公开(公告)号：US09830992B1
公开(公告)日：2017-11-28
申请号：US15362052
申请日：2016-11-28
发明人： Wen-Jer Tsai , Wei-Liang Lin , Chih-Chieh Cheng
CPC分类号： G11C16/26 , G11C11/5671 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/3445 , G11C16/3459
摘要： An operation method of a memory cell includes steps of applying a pre pulse before a read pulse is applied, wherein the pre pulse is larger than a maximum threshold voltage or less than a lowest threshold voltage.
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公开(公告)号：US09786794B2
公开(公告)日：2017-10-10
申请号：US15096044
申请日：2016-04-11
IPC分类号： H01L29/788 , H01L21/28 , H01L29/423 , H01L29/66 , H01L29/792 , H01L27/11551 , H01L27/11578
CPC分类号： H01L29/7887 , H01L21/28273 , H01L27/11551 , H01L27/11578 , H01L29/42332 , H01L29/66825 , H01L29/792 , H01L29/7923
摘要： A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.
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公开(公告)号：US20160225911A1
公开(公告)日：2016-08-04
申请号：US15096044
申请日：2016-04-11
IPC分类号： H01L29/788 , H01L29/423 , H01L21/28 , H01L29/66
CPC分类号： H01L29/7887 , H01L21/28273 , H01L27/11551 , H01L27/11578 , H01L29/42332 , H01L29/66825 , H01L29/792 , H01L29/7923
摘要： A memory structure includes a memory cell, and the memory cell includes following elements. A first gate is disposed on a substrate. A stacked structure includes a first dielectric structure, a channel layer, a second dielectric structure and a second gate disposed on the first gate, a first charge storage structure disposed in the first dielectric structure and a second charge storage structure disposed in the second dielectric structure. The first charge storage structure is a singular charge storage unit and the second charge storage structure comprises two charge storage units which are physically separated. A channel output line physically connected to the channel layer. A first dielectric layer is disposed on the first gate at two sides of the stacked structure. A first source or drain and a second source or drain are disposed on the first dielectric layer and located at two sides of the channel layer.
摘要翻译： 存储器结构包括存储单元，并且存储器单元包括以下元件。 第一栅极设置在基板上。 层叠结构包括第一电介质结构，沟道层，第二电介质结构和设置在第一栅极上的第二栅极，设置在第一介电结构中的第一电荷存储结构和设置在第二电介质结构中的第二电荷存储结构 。 第一电荷存储结构是单一电荷存储单元，并且第二电荷存储结构包括物理分离的两个电荷存储单元。 物理连接到通道层的通道输出线。 第一电介质层在堆叠结构的两侧设置在第一栅极上。 第一源极或漏极以及第二源极或漏极设置在第一介电层上并位于沟道层的两侧。
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公开(公告)号：US09385240B1
公开(公告)日：2016-07-05
申请号：US14637082
申请日：2015-03-03
发明人： Chih-Chieh Cheng , Shih-Guei Yan , Wen-Jer Tsai , Nan-Heng Lu
IPC分类号： H01L21/8239 , H01L27/105 , H01L29/792 , H01L27/115 , H01L21/266 , H01L23/528
CPC分类号： H01L29/7926 , H01L21/2253 , H01L21/26513 , H01L21/266 , H01L21/28282 , H01L23/528 , H01L27/11568 , H01L27/1157 , H01L2924/0002 , H01L2924/00
摘要： A memory device includes a substrate, a first doped region, composite structures, word lines, and a charge storage layer. The first doped region is disposed on a surface of the substrate. The composite structures are disposed on the first doped region. Each composite structure includes two semiconductor fin structures and a dielectric layer. Each semiconductor fin structure includes a second doped region disposed at an upper portion of the semiconductor fin structure and a body region disposed between the second doped region and the first doped region. The dielectric layer is disposed between the semiconductor fin structures. The word lines are disposed on the substrate. Each word line covers a partial sidewall and a partial top of each composite structure. The charge storage layer is disposed between the composite structures and the word lines.
摘要翻译： 存储器件包括衬底，第一掺杂区，复合结构，字线和电荷存储层。 第一掺杂区域设置在衬底的表面上。 复合结构设置在第一掺杂区域上。 每个复合结构包括两个半导体鳍结构和介电层。 每个半导体鳍结构包括设置在半导体鳍结构的上部的第二掺杂区和设置在第二掺杂区和第一掺杂区之间的体区。 电介质层设置在半导体鳍片结构之间。 字线设置在基板上。 每个字线覆盖每个复合结构的部分侧壁和部分顶部。 电荷存储层设置在复合结构和字线之间。
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公开(公告)号：US20140346586A1
公开(公告)日：2014-11-27
申请号：US14459050
申请日：2014-08-13
发明人： Chih-Chieh Cheng , Shih-Guei Yan , Wen-Jer Tsai
IPC分类号： H01L27/115 , H01L29/423
CPC分类号： H01L27/11563 , H01L21/28282 , H01L27/11568 , H01L29/4234 , H01L29/66833 , H01L29/792
摘要： A non-volatile memory structure, including a substrate, a plurality of stacked structures, a plurality of first conductive type doped regions, at least one second conductive type doped region, a conductive layer, and a first dielectric layer, is provided. The stacked structures are disposed on the substrate, and each of the stacked structures includes a charge storage structure. The first conductive type doped regions are disposed in the substrate under the corresponding charge storage structures respectively. The second conductive type doped region is disposed in the substrate between the adjacent charge storage structures and has an overlap region with each of the charge storage structures. The conductive layer covers the second conductive type doped region. The first dielectric layer is disposed between the conductive layer and the second conductive type doped region.
摘要翻译： 提供了包括基板，多个堆叠结构，多个第一导电型掺杂区域，至少一个第二导电型掺杂区域，导电层和第一介电层的非易失性存储器结构。 堆叠结构设置在基板上，并且每个堆叠结构都包括电荷存储结构。 第一导电型掺杂区域分别设置在相应的电荷存储结构下的衬底中。 第二导电型掺杂区域设置在相邻的电荷存储结构之间的衬底中，并且与每个电荷存储结构具有重叠区域。 导电层覆盖第二导电型掺杂区域。 第一介电层设置在导电层和第二导电型掺杂区之间。
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公开(公告)号：US20140308791A1
公开(公告)日：2014-10-16
申请号：US14314830
申请日：2014-06-25
IPC分类号： H01L29/66
CPC分类号： H01L29/66833 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/66825 , H01L29/7887 , H01L29/7923
摘要： A non-volatile memory and a manufacturing method thereof are provided. In this method, a first oxide layer having a protrusion is formed on a substrate. A pair of doped regions is formed in the substrate at two sides of the protrusion. A pair of charge storage spacers is formed on the sidewalls of the protrusion. A second oxide layer is formed on the first oxide layer and the pair of charge storage spacers. A conductive layer is formed on the second oxide layer, wherein the conductive layer is located completely on the top of the pair of charge storage spacers.
摘要翻译： 提供了一种非易失性存储器及其制造方法。 在该方法中，在基板上形成具有突出部的第一氧化物层。 在突起的两侧在衬底中形成一对掺杂区域。 在突起的侧壁上形成一对电荷存储间隔物。 在第一氧化物层和一对电荷存储间隔物上形成第二氧化物层。 导电层形成在第二氧化物层上，其中导电层完全位于一对电荷存储间隔物的顶部上。
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公开(公告)号：US20140264543A1
公开(公告)日：2014-09-18
申请号：US13869300
申请日：2013-04-24
发明人： Shih-Guei Yan , Wen-Jer Tsai , Chih-Chieh Cheng
IPC分类号： H01L21/308 , H01L29/792 , H01L29/66
CPC分类号： H01L27/11568 , H01L21/28282 , H01L29/66833 , H01L29/792
摘要： A semiconductor structure uses its control gate to be the wordline for receiving an operation voltage for the semiconductor structure. The semiconductor structure has a first and a second doped region and a buried channel between the first and the second doped region, wherein the buried channel has a first length along the first direction. The semiconductor structure further has a charge trapping layer stack on the buried channel and a conductive layer on the charge trapping layer stack, wherein the conductive layer extends along the first direction. The conductive layer is configured as both the control gate and the wordline of the semiconductor structure.
摘要翻译： 半导体结构使用其控制栅极作为用于接收半导体结构的工作电压的字线。 半导体结构在第一和第二掺杂区域之间具有第一和第二掺杂区域和掩埋沟道，其中所述掩埋沟道沿着第一方向具有第一长度。 半导体结构还在掩埋沟道上具有电荷俘获层堆叠，并且在电荷俘获层堆叠上具有导电层，其中导电层沿第一方向延伸。 导电层被配置为半导体结构的控制栅极和字线两者。
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