公开(公告)号：US10340017B2

公开(公告)日：2019-07-02

申请号：US15803986

申请日：2017-11-06

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Yu-Hung Huang ,  Cheng-Hsien Cheng ,  Chih-Wei Lee ,  Atsuhiro Suzuki ,  Wen-Jer Tsai

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/16 ,  G11C8/14

Abstract: An erase-verify method for a three-dimensional (3D) memory and a memory system are provided. The 3D memory includes at least one memory cell string including a plurality of memory cells, and the memory cells include a first group of memory cells and a second group of memory cells. Each of the memory cells is coupled to a word line. The method comprises the following steps. A first erase-verify operation is performed on the first group of memory cells. After performing the first erase-verify operation on the first group of memory cells, a second erase-verify operation is performed on the second group of memory cells in condition that the first group of memory cells are verified as erased successfully.

公开(公告)号：US11322207B1

公开(公告)日：2022-05-03

申请号：US17137461

申请日：2020-12-30

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Cheng-Hsien Cheng ,  Yu-Hung Huang ,  Chia-Hong Lee ,  Yin-Jen Chen

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/24

Abstract: A program method for a memory device is provided. The memory device includes a plurality of memory cells, a bit line and word lines electrically connected to the plurality of memory cells. The plurality of memory cells includes a selected memory cell and unselected memory cells when the memory device is in a program operation. The program method including performing precharge steps, performing program steps and performing a verification step to the selected memory cell after the precharge steps and the program steps. Each of the precharge steps includes applying a precharge voltage to the bit line electrically connected to the unselected memory cells. Each of the program steps includes applying a program voltage to a word line of the word lines electrically connected to the selected memory cell.

公开(公告)号：US11289132B1

公开(公告)日：2022-03-29

申请号：US17168215

申请日：2021-02-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Yu-Hung Huang ,  Cheng-Hsien Cheng ,  Chih-Chieh Cheng ,  Yin-Jen Chen

IPC: G11C7/00 ,  G11C11/00 ,  G11C5/14 ,  G11C8/08

Abstract: The present invention discloses an operation method of memory device, applied to a memory device including a number of word lines and one or more functional lines. The operation method includes: receiving a read command for a target memory cell of the memory device; and outputting a signal having a first waveform to a target word line corresponding to the target memory cell to be read among a plurality of the word lines of the memory device, output a signal having a second waveform to the one or more functional lines of the memory device, and output a signal having a third waveform to the word lines other than the target word line. A falling time of the third waveform is longer than a falling time of the first waveform.

公开(公告)号：US11037632B1

公开(公告)日：2021-06-15

申请号：US16828997

申请日：2020-03-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Chih-Chieh Cheng ,  Cheng-Hsien Cheng ,  Yu-Hung Huang ,  Atsuhiro Suzuki ,  Wen-Jer Tsai

IPC: G11C11/56 ,  G11C16/16 ,  G11C16/34 ,  G11C16/04

Abstract: Provided is an erase method for a multi-tier three-dimension (3D) memory including a plurality of tiers and a plurality of blocks, each of the tiers including a plurality of word lines. The erase method includes: in erasing a selected block among the plurality of blocks, in a current iteration, selecting at least one tier among the plurality of tiers to be erased by a first erase voltage; determining whether the at least one tier passes erase verification; and if the at least one tier passes erase verification, in a next iteration, inhibiting the at least tier which already passes erase verification from erase.

公开(公告)号：US11062759B1

公开(公告)日：2021-07-13

申请号：US16837041

申请日：2020-04-01

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Shaw-Hung Ku ,  Cheng-Hsien Cheng ,  Atsuhiro Suzuki ,  Yu-Hung Huang ,  Sheng-Kai Chen ,  Wen-Jer Tsai

IPC: G11C11/408 ,  G11C11/4074 ,  G11C11/56 ,  G11C11/409 ,  G11C11/4076

Abstract: A memory device and a programming method thereof are provided. The memory device includes a memory array, a plurality of word lines and a voltage generator. During a programming procedure, one of the word lines is at a selected state and others of the word lines are at a deselected state. Some of the word lines, which are at the deselected state, are classified into a first group and a second group. The first group and the second group are respectively located at two sides of the word line, which is at the selected state. The voltage generator provides a programming voltage to the word line, which is at the select state, during a programming duration. The voltage generator provides a first two-stage voltage waveform to the word lines in the first group and provides a second two-stage voltage waveform to the word lines in the second group.

公开(公告)号：US10796753B1

公开(公告)日：2020-10-06

申请号：US16667653

申请日：2019-10-29

Applicant: MACRONIX International Co., Ltd.

Inventor： Yu-Hung Huang ,  Cheng-Hsien Cheng ,  Shaw-Hung Ku ,  Yin-Jen Chen

IPC: G11C11/56 ,  G11C16/34 ,  G11C16/10

Abstract: A method for determining quick-pass-write (QPW) operation in increment-step-program-pulse (ISPP) operation is provided. The QPW operation is simultaneously applying a bit line voltage during the ISPP operation. The method includes, according to bit line voltages varying in a first range and voltage difference values varying in a second range with respect to a verified voltage, estimating a shrinkage quantity of threshold voltage distribution width at each bit line voltage and each voltage difference value, so as to obtain a shrinkage-quantity topographic contour. According to the bit line voltages and the voltage difference values, a program shot number as needed to achieve the verified voltage is estimated, so as to obtain a program-shot-number topographic contour. The shrinkage-quantity topographic contour and the program-shot-number topographic contour are overlapped to determine an operation region formed from an application range of the bit line voltage and an application range of the voltage difference value.