公开(公告)号：US20250014671A1

公开(公告)日：2025-01-09

申请号：US18403726

申请日：2024-01-04

Applicant: MACRONIX International Co., Ltd.

Inventor： You-Liang Chou ,  Wen-Jer Tsai

IPC: G11C29/52 ,  G11C16/24 ,  G11C16/26

Abstract: A memory device and a read method therefor are disclosed. The memory device includes first to third memory cell strings. The memory device is a three-dimensional NAND flash memory with high capacity and high performance. Each of the memory cell strings includes first to third memory cells. The read method includes: performing a first read operation of the memory device to the second memory cell in the second memory cell string, the first read operation includes applying a first bit line voltage to a first bit line, a second bit line, and a third bit line; in response to the failure of the first read operation, performing a second read operation of the memory device, the second read operation includes: applying a set of second bit line voltages to the first bit line, the second bit line and the third bit line.

公开(公告)号：US20250014650A1

公开(公告)日：2025-01-09

申请号：US18474228

申请日：2023-09-26

Applicant: MACRONIX International Co., Ltd.

Inventor： You-Liang Chou ,  Wen-Jer Tsai ,  Chih-Chieh Cheng

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

Abstract: A memory erase method for a memory device and a memory device therefore are provided. The memory device is a 3D NAND flash with high capacity and high performance. The memory erase method includes following steps: providing a memory block, wherein the memory block comprises memory cell strings, the memory cell strings include memory cells, string selection transistors and ground selection transistors; respectively applying corresponding erase voltages to corresponding word lines, a common source line, a corresponding bit line, the string selection transistor and the ground selection transistor of each of the memory cell strings. The voltage difference between a bit line erase voltage and a string selection line erase voltage or the voltage difference between the common source line erase voltage and the ground selection line erase voltage is less than or equal to a predetermined voltage difference, and the memory cells of the memory cell strings randomly classified as a type-1 erase bit or a type-2 erase bit.

公开(公告)号：US11990202B2

公开(公告)日：2024-05-21

申请号：US18047661

申请日：2022-10-19

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： You-Liang Chou ,  Wen-Jer Tsai

IPC: G11C29/52 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  H10B43/35

CPC classification number: G11C29/52 ,  G11C11/5671 ,  G11C16/08 ,  G11C16/10 ,  G11C16/0483 ,  H10B43/35

Abstract: A data recovery method is applied to a memory device which has a target memory cell, a target word line and an adjacent word line adjacent to the target word line. The target word line is connected to a gate of the target memory cell. The adjacent word line is connected to a gate of an adjacent memory cell, and the adjacent memory cell is adjacent to the target memory cell. In the data recovery method, a first program voltage is applied to the target memory cell through the target word line, and a second program voltage is concurrently applied to the adjacent memory cell through the adjacent word line.