公开(公告)号：US09929229B2

公开(公告)日：2018-03-27

申请号：US13219459

申请日：2011-08-26

Applicant: Kie Y. Ahn ,  Leonard Forbes

Inventor： Kie Y. Ahn ,  Leonard Forbes

IPC: H01F41/04 ,  H01F17/00 ,  H01L49/02 ,  H01L27/08 ,  H01P11/00 ,  H01P9/02 ,  H01F27/36

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F27/365 ,  H01F41/043 ,  H01F41/046 ,  H01L27/08 ,  H01P9/02 ,  H01P11/007 ,  Y10T29/4902 ,  Y10T29/4906 ,  Y10T29/49062 ,  Y10T29/49069 ,  Y10T29/49071 ,  Y10T29/49073 ,  Y10T29/49075

Abstract: Various embodiments includes a stacked open pattern inductor fabricated above a semiconductor substrate. The stacked open pattern inductor includes a plurality of parallel open conducting patterns embedded in a magnetic oxide or in an insulator and a magnetic material. A layer of magnetic material may be located above the inductor and below the inductor to confine electronic noise generated in the stacked open pattern inductor to the area occupied by the inductor. The stacked open pattern inductor may include a magnetic material directly contacts one of the conducting patterns and the substrate. The stacked open pattern inductor may be fabricated using conventional integrated circuit manufacturing processes, and the inductor may be used in connection with computer systems.

公开(公告)号：US09087730B2

公开(公告)日：2015-07-21

申请号：US13357347

申请日：2012-01-24

Applicant: Leonard Forbes

Inventor： Leonard Forbes

IPC: H01L29/66 ,  H01L27/108 ,  B82Y10/00 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L27/10876 ,  B82Y10/00 ,  H01L21/02532 ,  H01L21/823487 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10855 ,  H01L27/10879 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2924/13067

Abstract: One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. Other aspects are provided herein.

公开(公告)号：US08993455B2

公开(公告)日：2015-03-31

申请号：US12790598

申请日：2010-05-28

Applicant: Kie Y. Ahn ,  Leonard Forbes

Inventor： Kie Y. Ahn ,  Leonard Forbes

IPC: H01L21/31 ,  C23C16/455 ,  C23C16/30 ,  H01L21/314

CPC classification number: H01L21/02194 ,  C23C16/308 ,  C23C16/45531 ,  C23C16/45546 ,  H01L21/02178 ,  H01L21/02189 ,  H01L21/0228 ,  H01L21/28158 ,  H01L21/3143 ,  H01L28/40

Abstract: Atomic layer deposition (ALD) can be used to form a dielectric layer of zirconium aluminum oxynitride (ZrAlON) for use in a variety of electronic devices. Forming the dielectric layer may include depositing zirconium oxide using atomic layer deposition and precursor chemicals, followed by depositing aluminum nitride using precursor chemicals, and repeating. The dielectric layer may be used as the gate insulator of a MOSFET, a capacitor dielectric, and a tunnel gate insulator in flash memories.

Abstract translation: 原子层沉积（ALD）可用于形成用于各种电子器件的锆铝氮氧化物（ZrAlON）的介电层。 形成介电层可以包括使用原子层沉积和前体化学品沉积氧化锆，然后使用前体化学品沉积氮化铝并重复。 介质层可以用作闪存中的MOSFET，电容器电介质和隧道栅极绝缘体的栅极绝缘体。

公开(公告)号：US08686489B2

公开(公告)日：2014-04-01

申请号：US11472785

申请日：2006-06-22

Applicant: Leonard Forbes

Inventor： Leonard Forbes

IPC: H01L29/788

CPC classification number: H01L29/42324 ,  H01L21/28273

Abstract: The flash memory cell comprises a sense transistor that has a pair of source/drain lines and a control gate. A coupling metal-insulator-metal capacitor is created between the floating gate and a read wordline. A tunneling metal-insulator-metal capacitor is created between the floating gate and a write/erase bit line. In one embodiment, the insulator is a metal oxide.

Abstract translation: 闪存单元包括具有一对源极/漏极线和控制栅极的检测晶体管。 在浮动栅极和读取字线之间产生耦合金属 - 绝缘体 - 金属电容器。 在浮动栅极和写/擦除位线之间产生隧道式金属 - 绝缘体 - 金属电容器。 在一个实施例中，绝缘体是金属氧化物。

公开(公告)号：US08603907B2

公开(公告)日：2013-12-10

申请号：US13213911

申请日：2011-08-19

Applicant: Kie Y. Ahn ,  Leonard Forbes

Inventor： Kie Y. Ahn ,  Leonard Forbes

IPC: H01L21/3205 ,  H01L21/4763

CPC classification number: H01L21/02192 ,  C23C16/40 ,  C23C16/45529 ,  C23C16/4554 ,  C23C16/45553 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/28194 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/3142 ,  H01L21/31604 ,  H01L28/40 ,  H01L29/513 ,  H01L29/517 ,  H01L29/788 ,  H01L29/792

Abstract: Apparatus having a dielectric containing scandium and gadolinium can provide a reliable structure with a high dielectric constant (high k). In an embodiment, a monolayer or partial monolayer sequence process, such as for example atomic layer deposition (ALD), can be used to form a dielectric containing gadolinium oxide and scandium oxide. In an embodiment, a dielectric structure can be formed by depositing gadolinium oxide by atomic layer deposition onto a substrate surface using precursor chemicals, followed by depositing scandium oxide onto the substrate using precursor chemicals, and repeating to form a thin laminate structure. A dielectric containing scandium and gadolinium may be used as gate insulator of a MOSFET, a capacitor dielectric in a DRAM, as tunnel gate insulators in flash memories, as a NROM dielectric, or as a dielectric in other electronic devices, because the high dielectric constant (high k) of the film provides the functionality of a much thinner silicon dioxide film.

公开(公告)号：US08557672B2

公开(公告)日：2013-10-15

申请号：US13368206

申请日：2012-02-07

Applicant: Leonard Forbes ,  Kie Y. Ahn ,  Arup Bhattacharyya

Inventor： Leonard Forbes ,  Kie Y. Ahn ,  Arup Bhattacharyya

IPC: H01L21/20

CPC classification number: H01L21/02183 ,  C23C16/308 ,  C23C16/45525 ,  H01L21/02178 ,  H01L21/02194 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02307 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28273 ,  H01L21/3141 ,  H01L21/3145 ,  H01L21/31616 ,  H01L21/31637 ,  H01L28/60 ,  H01L28/65 ,  H01L29/518 ,  H01L29/7881

Abstract: Electronic apparatus and methods of forming the electronic apparatus may include one or more insulator layers having a refractory metal and a non-refractory metal for use in a variety of electronic systems and devices. Embodiments can include electronic apparatus and methods of forming the electronic apparatus having a tantalum aluminum oxynitride film. The tantalum aluminum oxynitride film may be structured as one or more monolayers. The tantalum aluminum oxynitride film may be formed using atomic layer deposition. Metal electrodes may be disposed on a dielectric containing a tantalum aluminum oxynitride film.

公开(公告)号：US08541276B2

公开(公告)日：2013-09-24

申请号：US13442140

申请日：2012-04-09

Applicant: Kie Y. Ahn ,  Leonard Forbes

Inventor： Kie Y. Ahn ,  Leonard Forbes

IPC: H01L21/336

CPC classification number: H01L21/0228 ,  C23C16/0281 ,  C23C16/40 ,  C23C16/45531 ,  H01L21/02178 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/022 ,  H01L21/02337 ,  H01L21/28229 ,  H01L21/3141 ,  H01L21/3142 ,  H01L29/513 ,  H01L29/517

Abstract: A dielectric containing an insulating metal oxide film having multiple metal components and a method of fabricating such a dielectric produce a reliable dielectric for use in a variety of electronic devices. Embodiments include a titanium aluminum oxide film structured as one or more monolayers. Embodiments also include structures for capacitors, transistors, memory devices, and electronic systems with dielectrics containing a titanium aluminum oxide film.

Abstract translation: 包含具有多个金属成分的绝缘金属氧化物膜的电介质和制造这种电介质的方法产生用于各种电子器件的可靠电介质。 实施方案包括被构造为一个或多个单层的钛氧化铝膜。 实施例还包括用于电容器，晶体管，存储器件和具有包含钛氧化铝膜的电介质的电子系统的结构。

公开(公告)号：US20130168803A1

公开(公告)日：2013-07-04

申请号：US13621737

申请日：2012-09-17

Applicant: Homayoon Haddad ,  Leonard Forbes

Inventor： Homayoon Haddad ,  Leonard Forbes

IPC: H01L21/50 ,  H01L29/16

CPC classification number: H01L21/50 ,  H01L21/6835 ,  H01L21/77 ,  H01L21/7806 ,  H01L29/16 ,  H01L2221/68327 ,  H01L2221/68363

Abstract: Semiconductor-on-insulator (SOI) devices and associated methods are provided. In one aspect, for example, a method for making a SOI device can include forming a device layer on a front side of a semiconductor layer, bonding a first substrate to the front side of the device layer, processing the semiconductor layer on a back side opposite the device layer to form a processed surface, and bonding a second substrate to the processed surface. In some aspects, the method can further include removing the first substrate from the front side to expose the device layer. In one aspect, forming the device layer can include forming optoelectronic circuitry at the front side of the semiconductor layer.

Abstract translation: 提供绝缘体上半导体（SOI）器件及相关方法。 一方面，例如，制造SOI器件的方法可以包括在半导体层的正面形成器件层，将第一衬底接合到器件层的前侧，在后侧处理半导体层 与所述器件层相对以形成经处理的表面，以及将第二衬底接合到所述经处理的表面。 在一些方面，该方法还可以包括从前侧去除第一衬底以暴露器件层。 一方面，形成器件层可以包括在半导体层的前侧形成光电子电路。

公开(公告)号：US08467639B2

公开(公告)日：2013-06-18

申请号：US13185074

申请日：2011-07-18

Applicant: Leonard Forbes ,  Kie Y. Ahn

Inventor： Leonard Forbes ,  Kie Y. Ahn

IPC: G02B6/12 ,  H01L21/00

CPC classification number: G02B6/43 ,  B82Y20/00 ,  G02B6/102 ,  H01L33/20 ,  H01L33/28

Abstract: The present disclosure includes methods, devices, and systems for zinc oxide diodes for optical interconnections. One system includes a ZnO emitter confined within a circular geometry in an oxide layer on a silicon substrate. An optical waveguide is formed in the oxide layer and has an input coupled to the ZnO emitter. A detector is coupled to an output of the optical waveguide.

公开(公告)号：US08409959B2

公开(公告)日：2013-04-02

申请号：US11717462

申请日：2007-03-13

Applicant: Badih El-Kareh ,  Leonard Forbes ,  Kie Y. Ahn

Inventor： Badih El-Kareh ,  Leonard Forbes ,  Kie Y. Ahn

IPC: H01L21/8222

CPC classification number: H01L29/732 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/66287 ,  H01L29/73 ,  H01L29/7371 ,  H03K17/60

Abstract: Methods, devices, and systems for using and forming vertically base-connected bipolar transistors have been shown. The vertically base-connected bipolar transistors in the embodiments of the present disclosure are formed with a CMOS fabrication technique that decreases the transistor size while maintaining the high performance characteristics of a bipolar transistor.