公开(公告)号：US20070183222A1

公开(公告)日：2007-08-09

申请号：US11700186

申请日：2007-01-31

申请人： Kohji Kanamori ,  Kenichi Kuboyama

发明人： Kohji Kanamori ,  Kenichi Kuboyama

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： H01L27/115 ,  G11C16/10

摘要： A programmable non-volatile semiconductor memory device includes a select gate 3, arranged in a first region on a substrate, a floating gate 6 arranged in a second region neighboring to the first region, a first diffusion region 7 provided in a third region neighboring to the second region, a control gate 11 arranged on the floating gate 6, and a driving circuit 22 adapted for controlling voltages applied to the substrate 1 (well 1a), select gate 3, first diffusion region 7 and control gate 11. The driving circuit performs control so that, during erasure operation, voltages applied to select gate 3 and the control gate 11 are negative, with the remaining voltage, applied to the substrate 1 (or well 1a), being positive. The device permits erasure operation at a lower voltage.

摘要翻译： 可编程非易失性半导体存储器件包括：布置在衬底上的第一区域中的选择栅极3，布置在与第一区域相邻的第二区域中的浮置栅极6，设置在与第一区域相邻的第三区域中的第一扩散区域7 第二区域，布置在浮置栅极6上的控制栅极11和适于控制施加到基板1（阱1a），选择栅极3，第一扩散区域7和控制栅极11的电压的驱动电路22。 电路进行控制，使得在擦除操作期间，施加到选择栅极3和控制栅极11的电压为负，而施加到衬底1（或阱1a）的剩余电压为正。 该器件允许在较低电压下的擦除操作。

公开(公告)号：US07619278B2

公开(公告)日：2009-11-17

申请号：US11410091

申请日：2006-04-25

申请人： Kenichi Kuboyama ,  Kohji Kanamori

发明人： Kenichi Kuboyama ,  Kohji Kanamori

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/7885

摘要： A semiconductor-memory device that reduces leak off due to miniaturization of memory cells, and comprises as a single unit cell: a substrate 1 having a trench section 1a; a selector gate 3 that is located via an insulating film 2 on the substrate adjacent to the trench section 1a; a first well 1b that is formed on the surface of the substrate 1 below the selector gate 3; a floating gate 6 that is located via an insulating film 8a on the surface of the bottom section and sidewall section of the trench section 1a; a second well 1c that is formed on the surface of the bottom section of the trench section 1a below the floating gate 6; a first diffusion area 7a that is formed on the surface of the bottom section of the trench section 1a; and a control gate 11 located via an insulating film 8 on top of the floating gate 6; and where the area near the sidewall surface and bottom surface of the trench section 1a forms a channel in the selector gate 3; and the impurity density of the first well 1b is not more than the impurity density of the second well 1c.

摘要翻译： 一种半导体存储器件，其减少由于存储单元的小型化而导致的泄漏，并且包括作为单个单元电池：具有沟槽部分1a的衬底1; 选择栅3，其经由与沟槽部1a相邻的基板上的绝缘膜2定位; 形成在选择栅3下方的基板1的表面上的第一阱1b; 位于沟槽部分1a的底部表面和侧壁部分的绝缘膜8a上的浮动栅极6; 形成在浮动栅极6下方的沟槽部分1a的底部表面上的第二阱1c; 在沟槽部分1a的底部表面上形成的第一扩散区域7a; 以及通过绝缘膜8位于浮动栅极6的顶部上的控制栅极11; 并且其中沟槽部分1a的侧壁表面和底表面附近的区域在选择器门3中形成通道; 并且第一阱1b的杂质浓度不大于第二阱1c的杂质浓度。

公开(公告)号：US07580293B2

公开(公告)日：2009-08-25

申请号：US11700186

申请日：2007-01-31

申请人： Kohji Kanamori ,  Kenichi Kuboyama

发明人： Kohji Kanamori ,  Kenichi Kuboyama

IPC分类号： G11C16/04

CPC分类号： H01L27/115 ,  G11C16/10

摘要： A programmable non-volatile semiconductor memory device includes a select gate 3, arranged in a first region on a substrate, a floating gate 6 arranged in a second region neighboring to the first region, a first diffusion region 7 provided in a third region neighboring to the second region, a control gate 11 arranged on the floating gate 6, and a driving circuit 22 adapted for controlling voltages applied to the substrate 1 (well 1a), select gate 3, first diffusion region 7 and control gate 11. The driving circuit performs control so that, during erasure operation, voltages applied to select gate 3 and the control gate 11 are negative, with the remaining voltage, applied to the substrate 1 (or well 1a), being positive. The device permits erasure operation at a lower voltage.

摘要翻译： 可编程非易失性半导体存储器件包括：布置在衬底上的第一区域中的选择栅极3，布置在与第一区域相邻的第二区域中的浮置栅极6，设置在与第一区域相邻的第三区域中的第一扩散区域7 第二区域，布置在浮置栅极6上的控制栅极11和适于控制施加到基板1（阱1a），选择栅极3，第一扩散区域7和控制栅极11的电压的驱动电路22。 执行控制，使得在擦除操作期间，施加到选择栅极3和控制栅极11的电压为负，而施加到衬底1（或阱1a）的剩余电压为正。 该器件允许在较低电压下的擦除操作。

公开(公告)号：US20060244040A1

公开(公告)日：2006-11-02

申请号：US11410091

申请日：2006-04-25

申请人： Kenichi Kuboyama ,  Kohji Kanamori

发明人： Kenichi Kuboyama ,  Kohji Kanamori

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/7885

摘要： A semiconductor-memory device that reduces leak off due to miniaturization of memory cells, and comprises as a single unit cell: a substrate 1 having a trench section 1a; a selector gate 3 that is located via an insulating film 2 on the substrate adjacent to the trench section 1a; a first well 1b that is formed on the surface of the substrate 1 below the selector gate 3; a floating gate 6 that is located via an insulating film 8a on the surface of the bottom section and sidewall section of the trench section 1a; a second well 1c that is formed on the surface of the bottom section of the trench section 1a below the floating gate 6; a first diffusion area 7a that is formed on the surface of the bottom section of the trench section 1a; and a control gate 11 located via an insulating film 8 on top of the floating gate 6; and where the area near the sidewall surface and bottom surface of the trench section 1a forms a channel in the selector gate 3; and the impurity density of the first well 1b is not more than the impurity density of the second well 1c.

摘要翻译： 一种半导体存储器件，其减小由于存储单元的小型化引起的泄漏，并且包括作为单个单元电池：具有沟槽部分1a的衬底1; 选择栅3，其经由与沟槽部1a相邻的基板上的绝缘膜2定位; 形成在选择栅3下方的基板1的表面上的第一阱1b; 位于沟槽部分1a的底部表面和侧壁部分的绝缘膜8a上的浮动栅极6; 形成在浮动栅极6下方的沟槽部分1a的底部表面上的第二阱1c; 形成在沟槽部1a的底部的表面上的第一扩散区域7a; 以及通过绝缘膜8位于浮动栅极6的顶部上的控制栅极11; 并且其中沟槽部分1a的侧壁表面和底表面附近的区域在选择器门3中形成通道; 并且第一阱1b的杂质浓度不大于第二阱1c的杂质浓度。

公开(公告)号：US10396092B2

公开(公告)日：2019-08-27

申请号：US15455778

申请日：2017-03-10

申请人： Kohji Kanamori ,  Dong-Seog Eun

发明人： Kohji Kanamori ,  Dong-Seog Eun

IPC分类号： H01L27/00 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565

摘要： Disclosed are vertical memory devices and methods of manufacturing the same. The vertical memory device may include includes a substrate, a gate stack structure and channel structure on the substrate, and a charge trap structure between the gate stack structure and the channel structure. The gate stack structure includes conductive structures and insulation interlayer structures that are alternately stacked on each other in a vertical direction on the substrate such that cell regions and inter-cell regions are alternately arranged in the vertical direction. The channel structure penetrates through the gate stack structure in the vertical direction. The charge trap structure and the conductive structures define memory cells at the cell regions. The charge structure is configured to selectively store charges. The charge trap structure includes an anti-coupling structure in the inter-cell region for reducing a coupling between neighboring memory cells adjacent to each other in the vertical direction.

公开(公告)号：US09183893B2

公开(公告)日：2015-11-10

申请号：US14037547

申请日：2013-09-26

申请人： Kohji Kanamori ,  Youngwoo Park ,  Jintaek Park ,  Kwang Soo Seol ,  Jaeduk Lee

发明人： Kohji Kanamori ,  Youngwoo Park ,  Jintaek Park ,  Kwang Soo Seol ,  Jaeduk Lee

IPC分类号： G11C5/06 ,  G11C13/00 ,  H01L45/00 ,  H01L27/22 ,  H01L27/24

CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C13/0002 ,  G11C13/0023 ,  G11C2213/73 ,  H01L27/222 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.

摘要翻译： 根据本发明构思的示例性实施例，半导体存储器件包括：多个存储器块，每个存储块包括多个堆叠结构，共同连接到多个存储器块的全局位线，被配置为控制 全局位线和多个存储器块中的一个以及垂直选择线，其被配置为控制连接在全局位线和多个堆叠结构中的一个之间的电连接。 多个堆叠结构中的每一个包括多个局部位线，第一垂直字线和第二垂直字线，其横向于多个堆叠结构的第一侧壁和第二侧壁相交，多个堆叠结构之间的第一可变电阻元件和 第一垂直字线和第二可变电阻元件在多个堆叠结构和第二垂直字线之间。

公开(公告)号：US08039940B2

公开(公告)日：2011-10-18

申请号：US11956358

申请日：2007-12-14

申请人： Kohji Kanamori ,  Teiichirou Nishizaka ,  Noriaki Kodama ,  Isao Katayama ,  Yoshihiro Matsuura ,  Kaoru Ishihara ,  Yasushi Harada ,  Naruaki Minenaga ,  Chihiro Oshita

发明人： Kohji Kanamori ,  Teiichirou Nishizaka ,  Noriaki Kodama ,  Isao Katayama ,  Yoshihiro Matsuura ,  Kaoru Ishihara ,  Yasushi Harada ,  Naruaki Minenaga ,  Chihiro Oshita

IPC分类号： H01L23/26

CPC分类号： H01L23/26 ,  H01L21/3221 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

摘要翻译： 根据本发明，在半导体芯片的侧表面和底表面上沉积吸气层。 然后将半导体芯片安装在封装的板上，使得在底表面上形成肖特基势垒。 通过这种结构，可以通过沉积在半导体芯片的侧表面和/或底表面上的缺陷层和肖特基势垒捕获穿过封装板的金属离子。

公开(公告)号：US07880214B2

公开(公告)日：2011-02-01

申请号：US11431569

申请日：2006-05-11

申请人： Naoaki Sudo ,  Kohji Kanamori

发明人： Naoaki Sudo ,  Kohji Kanamori

IPC分类号： H01L29/76

CPC分类号： H01L29/7887 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor storage device in which one unit cell comprises a select gate 3 (3a-3i) provided in a first region on a substrate 1; a floating gate 6 provided in a second region adjacent to the first region; a diffused region 7b adjacent to the second region and provided in a third region on the surface of the substrate 1; and a control gate 11 provided on the floating gate 6. The select gate 3 is divided into three or more in an erase block 23 composed of all unit cells, from each of which electrons are extracted from the floating gate, at the same time when an erase operation is performed. Each of the select gates 3a-3i, created by the division, is formed in a comb-like shape in which, when viewed from the direction of a normal line to a plane, a plurality of comb teeth extend from a common line. The comb teeth of a select gate (for example, 3b) are arranged in gaps between the comb teeth of an adjacent select gate (for example, 3a, 3c) at a predetermined spacing.

摘要翻译： 一种非易失性半导体存储装置，其中一个单位电池包括设置在基板1上的第一区域中的选择栅极3（3a-3i） 设置在与第一区域相邻的第二区域中的浮动栅极6; 与第二区域相邻并设置在基板1的表面的第三区域中的扩散区域7b; 以及设置在浮置栅极6上的控制栅极11.选择栅极3在由所有单位单元构成的擦除块23中被划分为三个或更多个，其中每一个从浮置栅极中提取电子，同时当 执行擦除操作。 通过分割产生的选择门3a-3i中的每一个形成为梳状形状，其中从法线方向看平面时，多条梳齿从公共线延伸。 选择门（例如3b）的梳齿以预定间隔布置在相邻选择栅极（例如，3a，3c）的梳齿之间的间隙中。

公开(公告)号：US07268385B2

公开(公告)日：2007-09-11

申请号：US10892553

申请日：2004-07-16

申请人： Teiichirou Nishizaka ,  Kohji Kanamori

发明人： Teiichirou Nishizaka ,  Kohji Kanamori

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0458 ,  G11C16/0491 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/7923

摘要： A semiconductor memory device comprises diffusion regions, a floating gate, a third diffusion region, a selection gate electrode, and a control gate electrode that three-dimensionally crosses the selection gate electrode and extends in a direction orthogonal to the selection gate electrode are included. A channel formed immediately below the selection gate and which constitutes a passage connecting the two diffusion regions has a shape in a top view, including a first path extending in one direction, from one diffusion region, and a second path extending from the end of the first path to the other diffusion region in a direction orthogonal to a first direction.

摘要翻译： 包括半导体存储器件，其包括扩散区域，浮置栅极，第三扩散区域，选择栅极电极和三维地穿过选择栅电极并沿与选择栅电极正交的方向延伸的控制栅电极。 形成在选择栅极正下方的通道，其构成连接两个扩散区域的通道，具有从一个扩散区域向一个扩散区域延伸的包括从一个方向延伸的第一路径和从第二路径延伸的第二路径的俯视图形状 在与第一方向正交的方向上的另一扩散区的第一路径。

公开(公告)号：US20070189077A1

公开(公告)日：2007-08-16

申请号：US11704934

申请日：2007-02-12

申请人： Kohji Kanamori

发明人： Kohji Kanamori

IPC分类号： G11C16/04 ,  G11C11/34 ,  G11C16/06

CPC分类号： H01L27/115 ,  G11C16/10 ,  H01L27/11521

摘要： A programmable non-volatile semiconductor memory device having which a sufficient operational margin with miniaturized memory cells. The memory device includes select gates 3, arranged in a first region on a substrate 1, floating gates 6, arranged in a second region, neighboring to the first region, first diffusion regions 7, arranged in a third region neighboring to the second region, and control gates 11 arranged above the floating gates 6. It also includes a driving circuit 22 for controlling the voltages applied to the substrate 1, select gates 3, first diffusion areas 7 and the controlling gates 11. At the time of reprogramming, the driving circuit 22 controls the voltages for first control and second control. The first control sets a low threshold voltage state, inclusive of the depletion state, for the bits, connected to a selected one of the control gates 11. The second control sets a low threshold voltage state or a high threshold voltage state of a desired enhancement state from one bit to another.

摘要翻译： 一种可编程的非易失性半导体存储器件，具有足够的操作余量与小型化的存储器单元。 存储装置包括选择栅极3，布置在基板1上的第一区域中，布置在与第一区域相邻的第二区域中的浮置栅极6布置在与第二区域相邻的第三区域中的第一扩散区域7， 以及布置在浮置栅极6上方的控制栅极11.它还包括用于控制施加到基板1，选择栅极3，第一扩散区域7和控制栅极11的电压的驱动电路22.在重新编程时，驱动 电路22控制用于第一控制和第二控制的电压。 第一控制器对连接到所选择的一个控制门11的位设置包括耗尽状态的低阈值电压状态。第二控制设置低阈值电压状态或期望增强的高阈值电压状态 状态从一点到另一位。