公开(公告)号：US08452913B2

公开(公告)日：2013-05-28

申请号：US12909060

申请日：2010-10-21

申请人： Naoaki Sudo

发明人： Naoaki Sudo

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/7205 ,  G06F2212/7209 ,  G06F2212/7211 ,  G11C16/16 ,  G11C16/349

摘要： A semiconductor memory device including a plurality of memory blocks, and an erase flag storage block storing erase flag information to indicate erase states of the plurality of memory blocks. The erase flag information can be used to monitor completion of erase operations of the memory blocks and to update erase count information of the memory blocks.

摘要翻译： 包括多个存储块的半导体存储器件以及擦除标志存储块，其存储用于指示多个存储块的擦除状态的擦除标志信息。 擦除标志信息可以用于监视存储块的擦除操作的完成并更新存储器块的擦除计数信息。

公开(公告)号：US20110145483A1

公开(公告)日：2011-06-16

申请号：US12909060

申请日：2010-10-21

申请人： Naoaki SUDO

发明人： Naoaki SUDO

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G06F12/0246 ,  G06F2212/7205 ,  G06F2212/7209 ,  G06F2212/7211 ,  G11C16/16 ,  G11C16/349

摘要： A semiconductor memory device comprises a plurality of memory blocks, and erase flag storage block storing erase flag information to indicate erase states of the plurality of memory blocks. The erase flag information can be used to monitor completion of erase operations of the memory blocks and to update erase count information of the memory blocks.

摘要翻译： 半导体存储器件包括多个存储器块，擦除标志存储块存储用于指示多个存储块的擦除状态的擦除标志信息。 擦除标志信息可以用于监视存储块的擦除操作的完成并更新存储器块的擦除计数信息。

公开(公告)号：US07936617B2

公开(公告)日：2011-05-03

申请号：US12341632

申请日：2008-12-22

申请人： Naoaki Sudo

发明人： Naoaki Sudo

IPC分类号： G11C5/14

CPC分类号： G11C16/30 ,  G11C5/147 ,  G11C8/08 ,  G11C16/08

摘要： Provided is a nonvolatile semiconductor memory device which can enhance a stable control of a voltage applied to a memory cell and has excellent capability of controlling a drain voltage. The nonvolatile semiconductor memory device includes: a plurality of memory cells; a write buffer receiving data to be written to the plurality of memory cells; a count circuit searching data input to the write buffer and determining bit number of data to be simultaneously programmed to the plurality of memory cells; a write circuit supplying a write voltage to the plurality of memory cells according to the data; and a voltage regulator supplying a control voltage (Vpb) to the write circuit, wherein the voltage regulator includes a controller Counting write bit number and supplying the control voltage (Vpb) according to the counted write bit number.

摘要翻译： 提供了一种非易失性半导体存储器件，其可以增强对存储单元施加的电压的稳定控制，并且具有优异的控制漏极电压的能力。 非易失性半导体存储器件包括：多个存储单元; 写入缓冲器，接收要写入多个存储器单元的数据; 搜索输入到写缓冲器的数据的计数电路，并确定要同时编程到多个存储器单元的数据的位数; 写入电路，根据该数据向多个存储单元提供写入电压; 以及向写入电路提供控制电压（Vpb）的电压调节器，其中所述电压调节器包括控制器对写入位数进行计数，并根据所述计数的写入位数提供所述控制电压（Vpb）。

公开(公告)号：US07453117B2

公开(公告)日：2008-11-18

申请号：US11453796

申请日：2006-06-16

申请人： Naoaki Sudo ,  Kohji Kanamori

发明人： Naoaki Sudo ,  Kohji Kanamori

IPC分类号： H01L29/76

CPC分类号： H01L29/7887 ,  G11C16/0441 ,  G11C16/0491 ,  G11C16/28 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

摘要： To achieve a high-speed and reliable read operation. A unit cell is constituted by a select gate 3 provided in a first region and on a substrate 1 with an insulating film 2 interposed inbetween, a floating gate 6a provided in a second region adjacent to the first region with an insulating film 5 interposed inbetween, a diffusion region 7a provided in a third region adjacent to the second region and on the surface of the substrate, and a control gate 11 provided on the top of the floating gate 6a with an insulating film 8 interposed inbetween. Each data bit is stored using corresponding first unit cell and second unit cell.

摘要翻译： 实现高速可靠的读取操作。 单位电池由设置在第一区域中的选择栅极3和介于其间的绝缘膜2的基板1构成，设置在与第一区域相邻的第二区域中的浮置栅极6a与介于其间的绝缘膜5 设置在与第二区域相邻的第三区域和衬底的表面上的扩散区域7a，以及设置在浮置栅极6a的顶部上的绝缘膜8的控制栅极11。 使用对应的第一单元单元和第二单元单元存储每个数据位。

公开(公告)号：US06456549B1

公开(公告)日：2002-09-24

申请号：US09938968

申请日：2001-08-24

申请人： Naoaki Sudo ,  Hiroyuki Takahashi

发明人： Naoaki Sudo ,  Hiroyuki Takahashi

IPC分类号： G11C700

CPC分类号： G11C7/065

摘要： According to one embodiment, a latch-type sense amplifier can reduce noise at a signal input that may be generated by capacitive coupling of a sense amplifier latch enable signal. A latch-type sense amplifier may include a first transfer gate TG1 between a first input SA1 and a first latch node N1, and a second transfer gate TG2 between a second input SA2 and a second latch node N2. A first transfer gate may include complementary transistors NM1 and PM1. Transistor NM1 can receive a control signal /SE at a control gate while transistor PM1 can receive a complementary control signal SE at a control gate. Transistor NM1 may include a parasitic capacitance C0N and transistor PM1 may include a parasitic capacitance C0P that is essentially equivalent to C0N. In such an arrangement, noise at first input SA1 generated by capacitive coupling of a control signal SE can be reduced and/or cancelled by noise generated by capacitive coupling of a complementary control signal /SE.

公开(公告)号：US6141262A

公开(公告)日：2000-10-31

申请号：US287285

申请日：1999-04-07

申请人： Naoaki Sudo

发明人： Naoaki Sudo

IPC分类号： G11C11/413 ,  G11C8/08 ,  G11C11/407 ,  G11C16/06 ,  G11C16/08 ,  H01L21/822 ,  H01L27/04 ,  H02M3/07 ,  G11C7/00

CPC分类号： G11C8/08 ,  G11C16/08

摘要： A boosting circuit includes a plurality of boosting circuit units, a voltage detecting circuit and a boost control circuit. The plurality of boosting circuit units have their outputs connected together and respectively having voltage boosting functions. Each of the plurality of boosting circuit units generates a boosted voltage higher than a power supply voltage in response to a drive signal. The voltage detecting circuit detects whether or not the boosted voltage is higher than a predetermined voltage, to generate a voltage control signal when it is detected that the boosted voltage is higher than a predetermined voltage. The boost control circuit limits the voltage boosting functions of predetermined ones of the plurality of boosting circuit units in response to the voltage control signal.

摘要翻译： 升压电路包括多个升压电路单元，电压检测电路和升压控制电路。 多个升压电路单元的输出端连接在一起，分别具有升压功能。 多个升压电路单元中的每一个响应于驱动信号产生比电源电压高的升压电压。 电压检测电路检测升压电压是否高于预定电压，当检测到升压电压高于预定电压时产生电压控制信号。 升压控制电路响应于电压控制信号来限制多个升压电路单元中的预定升压电路单元的升压功能。

公开(公告)号：US6094374A

公开(公告)日：2000-07-25

申请号：US272344

申请日：1999-03-19

申请人： Naoaki Sudo

发明人： Naoaki Sudo

IPC分类号： G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  G11C16/28 ,  G11C16/34

CPC分类号： G11C16/3481 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/3468 ,  G11C2211/5624 ,  G11C7/06

摘要： The object of the present invention is to reduce the dispersion of the threshold after writing while maintaining the high speed nature of a write system in a nonvolatile semiconductor memory such as a flash memory of channel hot electron write type. The feature of this invention is to provide a memory with a write current detection type write circuit and a sense amplifier for read, and to switch, for verification at the time of write, between verification by the write current type write circuit and verification of normal read mode which uses the sense amplifier for read. In other words, when a cell threshold of write level is designated as a first threshold and a specified threshold level lower than the first threshold is designated as a second threshold, write operation by the write current detection type write circuit is performed at the beginning of write mode, and stops the write operation when the current flowing between the drain and the source of the memory cell falls to below or equal to the reference current corresponding to the second threshold. Thereafter, the write operation is performed by repeating the write operation and verification operation using the sense amplifier until the cell threshold reaches the first threshold.

摘要翻译： 本发明的目的是为了减少写入之后的阈值的偏差，同时将诸如通道热电子写入型闪存的非易失性半导体存储器中的写入系统的高速性保持在一起。 本发明的特征在于提供具有写入电流检测型写入电路和读出放大器的存储器，用于在写入时由写入电流型写入电路的验证和正常的验证之间进行读取和切换，以进行验证 读取模式，使用读出放大器进行读取。 换句话说，当写入电平的单元阈值被指定为第一阈值且低于第一阈值的指定阈值被指定为第二阈值时，写入电流检测型写入电路的写入操作在 写入模式，并且当在存储器单元的漏极和源极之间流动的电流降至或等于对应于第二阈值的参考电流时停止写入操作。 此后，通过使用读出放大器重复写入操作和验证操作来执行写入操作，直到单元阈值达到第一阈值。

公开(公告)号：US20060267076A1

公开(公告)日：2006-11-30

申请号：US11442296

申请日：2006-05-30

申请人： Naoaki Sudo

发明人： Naoaki Sudo

IPC分类号： H01L29/788

CPC分类号： G11C16/28 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529

摘要： Disclosed is to enable high speed reading from a storage node when a read is executed. A main cell array is constituted from main cell division units 20a. Each main cell division unit 20a includes select gates SG that extend in a vertical direction, common sources CS that extend in a horizontal direction below the select gates SG outside a cell region, word lines W0 to W15 that extend above the select gates SG in the horizontal direction within the cell region, a plurality of storage nodes disposed in the vicinity of intersecting portions between the word lines W0 to W15 and the select gates SG, respectively, below the word lines W0 to W15, and a bit line MGB for transmitting to a sense amplifier 11 information on one of the storage nodes through a selection switch 21. In the main cell division unit 20a, an inversion layer is formed below each of the select gates SG within the cell region by applying a positive voltage to each of the select gates SG. A reference cell array is constituted from a reference cell division unit 30a having a same configuration as the main cell division unit 20a.

摘要翻译： 公开了当执行读取时能够从存储节点进行高速读取。 主单元阵列由主单元分割单元20a构成。 每个主单元划分单元20a包括在垂直方向上延伸的选择栅极SG，在单元区域外的选择栅极SG下方沿水平方向延伸的公共源CS，在选择栅极上方延伸的字线W 0至W 15 SG在单元区域内的水平方向上分别设置有多个存储节点，分别设置在字线W 0至W 15和选择栅极SG之间的相交部分附近，位于字线W 0至W 15的下方，以及 位线MGB用于通过选择开关21向存储放大器11发送关于其中一个存储节点的信息。在主单元划分单元20a中，在单元区域内的每个选择栅极SG下方形成反型层， 向每个选择栅极SG施加正电压。 参考单元阵列由具有与主单元划分单元20a相同配置的参考单元划分单元30a构成。

公开(公告)号：US06301180B1

公开(公告)日：2001-10-09

申请号：US09660869

申请日：2000-09-13

申请人： Naoaki Sudo ,  Hiroyuki Takahashi

发明人： Naoaki Sudo ,  Hiroyuki Takahashi

IPC分类号： G11C702

CPC分类号： G11C7/065

摘要： According to one embodiment, a latch-type sense amplifier can reduce noise at a signal input that may be generated by capacitive coupling of a sense amplifier latch enable signal. A latch-type sense amplifier may include a first transfer gate TG1 between a first input SA1 and a first latch node N1, and a second transfer gate TG2 between a second input SA2 and a second latch node N2. A first transfer gate may include complementary transistors NM1 and PM1. Transistor NM1 can receive a control signal /SE at a control gate while transistor PM1 can receive a complementary control signal SE at a control gate. Transistor NM1 may include a parasitic capacitance C0N and transistor PM1 may include a parasitic capacitance C0P that is essentially equivalent to C0N. In such an arrangement, noise at first input SA1 generated by capacitive coupling of a control signal SE can be reduced and/or cancelled by noise generated by capacitive coupling of a complementary control signal /SE.

摘要翻译： 根据一个实施例，锁存型读出放大器可以减小可能由读出放大器锁存使能信号的电容耦合产生的信号输入处的噪声。 锁存型读出放大器可以包括在第一输入SA1和第一锁存节点N1之间的第一传输门TG1和第二输入SA2与第二锁存节点N2之间的第二传输门TG2。 第一传输门可以包括互补晶体管NM1和PM1。 晶体管NM1可以在控制栅极处接收控制信号/ SE，而晶体管PM1可以在控制栅极处接收互补的控制信号SE。 晶体管NM1可以包括寄生电容C0N，并且晶体管PM1可以包括基本上等于C0N的寄生电容C0P。 在这种布置中，通过控制信号SE的电容耦合产生的第一输入端SA1的噪声可以通过互补控制信号/ SE的电容耦合产生的噪声来减小和/或抵消。

公开(公告)号：US07880214B2

公开(公告)日：2011-02-01

申请号：US11431569

申请日：2006-05-11

申请人： Naoaki Sudo ,  Kohji Kanamori

发明人： Naoaki Sudo ,  Kohji Kanamori

IPC分类号： H01L29/76

CPC分类号： H01L29/7887 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A nonvolatile semiconductor storage device in which one unit cell comprises a select gate 3 (3a-3i) provided in a first region on a substrate 1; a floating gate 6 provided in a second region adjacent to the first region; a diffused region 7b adjacent to the second region and provided in a third region on the surface of the substrate 1; and a control gate 11 provided on the floating gate 6. The select gate 3 is divided into three or more in an erase block 23 composed of all unit cells, from each of which electrons are extracted from the floating gate, at the same time when an erase operation is performed. Each of the select gates 3a-3i, created by the division, is formed in a comb-like shape in which, when viewed from the direction of a normal line to a plane, a plurality of comb teeth extend from a common line. The comb teeth of a select gate (for example, 3b) are arranged in gaps between the comb teeth of an adjacent select gate (for example, 3a, 3c) at a predetermined spacing.

摘要翻译： 一种非易失性半导体存储装置，其中一个单位电池包括设置在基板1上的第一区域中的选择栅极3（3a-3i） 设置在与第一区域相邻的第二区域中的浮动栅极6; 与第二区域相邻并设置在基板1的表面的第三区域中的扩散区域7b; 以及设置在浮置栅极6上的控制栅极11.选择栅极3在由所有单位单元构成的擦除块23中被划分为三个或更多个，其中每一个从浮置栅极中提取电子，同时当 执行擦除操作。 通过分割产生的选择门3a-3i中的每一个形成为梳状形状，其中从法线方向看平面时，多条梳齿从公共线延伸。 选择门（例如3b）的梳齿以预定间隔布置在相邻选择栅极（例如，3a，3c）的梳齿之间的间隙中。