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    SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL AND AIR GAP, AND METHOD OF MANUFACTURING THEREOF
    2.
    发明申请
    SEMICONDUCTOR DEVICE HAVING VERTICAL CHANNEL AND AIR GAP, AND METHOD OF MANUFACTURING THEREOF 有权
    具有垂直通道和空气隙的半导体器件及其制造方法

    公开(公告)号：US20150380431A1

    公开(公告)日：2015-12-31

    申请号：US14642086

    申请日：2015-03-09

    申请人： KOHJI KANAMORI ,  CHUNG-JIN KIM ,  YOUNG-WOO PARK ,  JAE-GOO LEE ,  JAE-DUK LEE ,  MOO-RYM CHOI

    发明人： KOHJI KANAMORI ,  CHUNG-JIN KIM ,  YOUNG-WOO PARK ,  JAE-GOO LEE ,  JAE-DUK LEE ,  MOO-RYM CHOI

    IPC分类号： H01L27/115 ,  H01L23/528 ,  H01L23/532 ,  H01L29/792

    CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/1157

    摘要： A semiconductor device is provided. Word lines are formed on a substrate. An air gap is interposed between two adjacent word lines. A channel structure penetrates through the word lines and the air gap. A memory cell is interposed between each word line and the channel structure. The memory cell includes a blocking pattern, a charge trap pattern and a tunneling insulating pattern. The blocking pattern conformally covers a top surface, a bottom surface, and a first side surface of each word line. The first side surface is adjacent to the channel structure. The charge trap pattern is interposed only between the first side surface and the channel structure.

    摘要翻译： 提供半导体器件。 字线形成在基板上。 在两个相邻字线之间插入气隙。 通道结构穿过字线和气隙。 存储单元插入在每个字线和通道结构之间。 存储单元包括阻挡图案，电荷陷阱图案和隧道绝缘图案。 阻挡图案保形地覆盖每个字线的顶表面，底表面和第一侧表面。 第一侧表面与通道结构相邻。 电荷陷阱图案仅插入在第一侧表面和沟道结构之间。

    SEMICONDUCTOR MEMORY DEVICE
    4.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权
    半导体存储器件

    公开(公告)号：US20140085961A1

    公开(公告)日：2014-03-27

    申请号：US14037547

    申请日：2013-09-26

    申请人： Kohji KANAMORI ,  Youngwoo PARK ,  Jintaek PARK ,  Kwang Soo SEOL ,  Jaeduk LEE

    发明人： Kohji KANAMORI ,  Youngwoo PARK ,  Jintaek PARK ,  Kwang Soo SEOL ,  Jaeduk LEE

    IPC分类号： G11C5/06 ,  G11C13/00

    CPC分类号： G11C5/06 ,  G11C5/063 ,  G11C13/0002 ,  G11C13/0023 ,  G11C2213/73 ,  H01L27/222 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

    摘要： According to example embodiments of inventive concepts, a semiconductor memory devices includes: a plurality of memory blocks that each include a plurality of stack structures, global bit lines connected in common to the plurality of memory blocks, block selection lines configured to control electrical connect between the global bit lines and one of the plurality of memory blocks, and vertical selection lines configured to control electrical connected between the global bit lines and one of the plurality of stack structures. Each of the plurality of stack structures includes a plurality of local bit lines, first vertical word lines and second vertical word lines crossing first sidewalls and second sidewalls respectfully of the plurality of stack structures, first variable resistive elements between the plurality of stack structures and the first vertical word lines, and second variable resistive elements between the plurality of stack structures and the second vertical word lines.

    摘要翻译： 根据本发明构思的示例性实施例，半导体存储器件包括：多个存储器块，每个存储块包括多个堆叠结构，共同连接到多个存储器块的全局位线，被配置为控制 全局位线和多个存储器块中的一个以及垂直选择线，其被配置为控制连接在全局位线和多个堆叠结构中的一个之间的电连接。 多个堆叠结构中的每一个包括多个局部位线，第一垂直字线和第二垂直字线，其横向于多个堆叠结构的第一侧壁和第二侧壁相交，多个堆叠结构之间的第一可变电阻元件和 第一垂直字线和第二可变电阻元件在多个堆叠结构和第二垂直字线之间。

    Non-volatile semiconductor memory device
    5.
    发明授权
    Non-volatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US07453117B2

    公开(公告)日：2008-11-18

    申请号：US11453796

    申请日：2006-06-16

    申请人： Naoaki Sudo ,  Kohji Kanamori

    发明人： Naoaki Sudo ,  Kohji Kanamori

    IPC分类号： H01L29/76

    CPC分类号： H01L29/7887 ,  G11C16/0441 ,  G11C16/0491 ,  G11C16/28 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/66825

    摘要： To achieve a high-speed and reliable read operation. A unit cell is constituted by a select gate 3 provided in a first region and on a substrate 1 with an insulating film 2 interposed inbetween, a floating gate 6a provided in a second region adjacent to the first region with an insulating film 5 interposed inbetween, a diffusion region 7a provided in a third region adjacent to the second region and on the surface of the substrate, and a control gate 11 provided on the top of the floating gate 6a with an insulating film 8 interposed inbetween. Each data bit is stored using corresponding first unit cell and second unit cell.

    摘要翻译： 实现高速可靠的读取操作。 单位电池由设置在第一区域中的选择栅极3和介于其间的绝缘膜2的基板1构成，设置在与第一区域相邻的第二区域中的浮置栅极6a与介于其间的绝缘膜5 设置在与第二区域相邻的第三区域和衬底的表面上的扩散区域7a，以及设置在浮置栅极6a的顶部上的绝缘膜8的控制栅极11。 使用对应的第一单元单元和第二单元单元存储每个数据位。

    Semiconductor memory device
    6.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07411838B2

    公开(公告)日：2008-08-12

    申请号：US11700184

    申请日：2007-01-31

    申请人： Kohji Kanamori

    发明人： Kohji Kanamori

    IPC分类号： G11C16/04

    CPC分类号： H01L27/11524 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521

    摘要： A drive circuit 22 controls voltages applied to a substrate 1, selection gates SG0 and SG1, a local bit line LB2, and a control gate CGn. By respectively applying a negative voltage to the control gate CGn, a positive voltage to the selection gate SG0, a voltage lower than the voltage applied to the selection gate SG0 to the selection gate SG1, and a positive voltage to the local bit line LB2, the drive circuit 22 controls so that electrons are selectively drawn out of a floating gate FG3 to the local bit line LB2 by F-N tunneling during writing operation. Sufficient operation margin is obtained even when memory cells are miniaturized.

    摘要翻译： 驱动电路22控制施加到基板1，选择栅极SG0和SG1，局部位线LB2和控制栅极CGn的电压。 通过分别对控制栅极CGn施加负电压，向选择栅极SG0施加正电压，低于施加到选择栅极SG0的电压至选择栅极SG1的电压，以及对该局部位置的正电压 线路LB2，驱动电路22进行控制，使得在写入操作期间，通过FN隧穿，电子被选择性地从浮动栅极FG3拉出到局部位线LB 2。 即使存储单元小型化，也能获得足够的操作余量。

    Nonvolatile semiconductor memory device and method of programming in nonvolatile semiconductor memory device
    8.
    发明申请
    Nonvolatile semiconductor memory device and method of programming in nonvolatile semiconductor memory device 有权
    非易失性半导体存储器件和非易失性半导体存储器件中的编程方法

    公开(公告)号：US20050185470A1

    公开(公告)日：2005-08-25

    申请号：US11059382

    申请日：2005-02-17

    申请人： Junichi Suzuki ,  Kohji Kanamori

    发明人： Junichi Suzuki ,  Kohji Kanamori

    IPC分类号： G11C16/02 ,  G11C11/34 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

    CPC分类号： G11C16/3468 ,  G11C16/12

    摘要： A memory cell array includes a plurality of memory cells each of which has a control gate and a floating gate. A programming circuit operates in a first programming mode followed by a second programming mode. In the first programming mode, the programming circuit applies a first program pulse to first memory cells while progressively increasing a programming capability of the first program pulse until threshold voltages of the first memory cells become higher than or equal to a first reference voltage. In the second programming mode, the programming circuit applies a second program pulse to second memory cells included in the first memory cells and having threshold voltages lower than a second reference voltage that is higher than the first reference voltage until the threshold voltages of the second memory cells become higher than or equal to the second reference voltage.

    摘要翻译： 存储单元阵列包括多个存储单元，每个存储单元具有控制栅极和浮置栅极。 编程电路以第一编程模式工作，随后是第二编程模式。 在第一编程模式中，编程电路将第一编程脉冲施加到第一存储单元，同时逐渐增加第一编程脉冲的编程能力，直到第一存储单元的阈值电压变为高于或等于第一参考电压。 在第二编程模式中，编程电路将第二编程脉冲施加到包括在第一存储单元中的第二存储单元，并具有低于高于第一参考电压的第二参考电压的阈值电压，直到第二存储器的阈值电压 单元变得高于或等于第二参考电压。

    Semiconductor memory and manufacturing method thereof
    9.
    发明授权
    Semiconductor memory and manufacturing method thereof 失效
    半导体存储器及其制造方法

    公开(公告)号：US06414346B1

    公开(公告)日：2002-07-02

    申请号：US09767568

    申请日：2001-01-23

    申请人： Kohji Kanamori

    发明人： Kohji Kanamori

    IPC分类号： H01L27108

    CPC分类号： H01L27/11521 ,  H01L27/115

    摘要： A semiconductor memory is provided with a memory cell region and a peripheral circuit region. The memory cell region includes semiconductor memory cells arranged in an array and element separating shield electrodes. The element separating shield electrodes extend in a column direction and separate semiconductor memory cells being adjacent to each other in a row direction. Further, a peripheral circuit sending and receiving data to and from the semiconductor memory cell is provided in the peripheral circuit region. Elements in the peripheral circuit are separated by an element separation insulating film. The element separating shield electrodes extend onto the element separation insulating film at a boundary between the memory cell region and the peripheral circuit region.

    摘要翻译： 半导体存储器设置有存储单元区域和外围电路区域。 存储单元区域包括排列成阵列的半导体存储单元和隔离屏蔽电极的元件。 分离屏蔽电极的元件在列方向上延伸，并且在行方向上分离彼此相邻的半导体存储单元。 此外，在外围电路区域中提供向半导体存储单元发送数据和从半导体存储单元接收数据的外围电路。 外围电路中的元件由元件隔离绝缘膜分开。 分离屏蔽电极的元件在存储单元区域和外围电路区域之间的边界处延伸到元件隔离绝缘膜上。

    Semiconductor device with no step between well regions
    10.
    发明授权
    Semiconductor device with no step between well regions 失效
    半导体器件在阱区之间没有一步

    公开(公告)号：US06201274B1

    公开(公告)日：2001-03-13

    申请号：US09179392

    申请日：1998-10-27

    申请人： Kohji Kanamori

    发明人： Kohji Kanamori

    IPC分类号： H01L2976

    CPC分类号： H01L27/11526 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823892 ,  H01L27/092 ,  H01L27/105 ,  H01L27/11529 ,  H01L27/11546

    摘要： In a semiconductor device having a high voltage transistor, a first well region of the high voltage transistor is formed in a semiconductor substrate as a channel region. The first well region has a first conductive type. Second well regions of the high voltage transistor are formed in the semiconductor substrate as a source region and a drain region to sandwich the first well region. The second well region has a second conductive type. A surface of the first region and surfaces of the second well regions have a flat plane.

    摘要翻译： 在具有高电压晶体管的半导体器件中，高压晶体管的第一阱区形成在半导体衬底中作为沟道区。 第一阱区具有第一导电类型。 在半导体衬底中形成高压晶体管的第二阱区作为源极区和漏极区以夹持第一阱区。 第二阱区具有第二导电类型。 第一区域的表面和第二阱区域的表面具有平坦的平面。