公开(公告)号：US08039940B2

公开(公告)日：2011-10-18

申请号：US11956358

申请日：2007-12-14

申请人： Kohji Kanamori ,  Teiichirou Nishizaka ,  Noriaki Kodama ,  Isao Katayama ,  Yoshihiro Matsuura ,  Kaoru Ishihara ,  Yasushi Harada ,  Naruaki Minenaga ,  Chihiro Oshita

发明人： Kohji Kanamori ,  Teiichirou Nishizaka ,  Noriaki Kodama ,  Isao Katayama ,  Yoshihiro Matsuura ,  Kaoru Ishihara ,  Yasushi Harada ,  Naruaki Minenaga ,  Chihiro Oshita

IPC分类号： H01L23/26

CPC分类号： H01L23/26 ,  H01L21/3221 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

摘要翻译： 根据本发明，在半导体芯片的侧表面和底表面上沉积吸气层。 然后将半导体芯片安装在封装的板上，使得在底表面上形成肖特基势垒。 通过这种结构，可以通过沉积在半导体芯片的侧表面和/或底表面上的缺陷层和肖特基势垒捕获穿过封装板的金属离子。

公开(公告)号：US07268385B2

公开(公告)日：2007-09-11

申请号：US10892553

申请日：2004-07-16

申请人： Teiichirou Nishizaka ,  Kohji Kanamori

发明人： Teiichirou Nishizaka ,  Kohji Kanamori

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0458 ,  G11C16/0491 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/7923

摘要： A semiconductor memory device comprises diffusion regions, a floating gate, a third diffusion region, a selection gate electrode, and a control gate electrode that three-dimensionally crosses the selection gate electrode and extends in a direction orthogonal to the selection gate electrode are included. A channel formed immediately below the selection gate and which constitutes a passage connecting the two diffusion regions has a shape in a top view, including a first path extending in one direction, from one diffusion region, and a second path extending from the end of the first path to the other diffusion region in a direction orthogonal to a first direction.

摘要翻译： 包括半导体存储器件，其包括扩散区域，浮置栅极，第三扩散区域，选择栅极电极和三维地穿过选择栅电极并沿与选择栅电极正交的方向延伸的控制栅电极。 形成在选择栅极正下方的通道，其构成连接两个扩散区域的通道，具有从一个扩散区域向一个扩散区域延伸的包括从一个方向延伸的第一路径和从第二路径延伸的第二路径的俯视图形状 在与第一方向正交的方向上的另一扩散区的第一路径。

公开(公告)号：US20080099883A1

公开(公告)日：2008-05-01

申请号：US11956358

申请日：2007-12-14

申请人： Kohji KANAMORI ,  Teiichirou Nishizaka ,  Noriaki Kodama ,  Isao Katayama ,  Yoshihiro Matsuura ,  Kaoru Ishihara ,  Yasushi Harada ,  Naruaki Minenaga ,  Chihiro Oshita

发明人： Kohji KANAMORI ,  Teiichirou Nishizaka ,  Noriaki Kodama ,  Isao Katayama ,  Yoshihiro Matsuura ,  Kaoru Ishihara ,  Yasushi Harada ,  Naruaki Minenaga ,  Chihiro Oshita

IPC分类号： H01L29/30

CPC分类号： H01L23/26 ,  H01L21/3221 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

摘要翻译： 根据本发明，在半导体芯片的侧表面和底表面上沉积吸气层。 然后将半导体芯片安装在封装的板上，使得在底表面上形成肖特基势垒。 通过这种结构，可以通过沉积在半导体芯片的侧表面和/或底表面上的缺陷层和肖特基势垒捕获穿过封装板的金属离子。

公开(公告)号：US07064382B2

公开(公告)日：2006-06-20

申请号：US11074064

申请日：2005-03-08

申请人： Noriaki Kodama ,  Kohji Kanamori ,  Junichi Suzuki ,  Teiichirou Nishizaka ,  Yasuhide Den ,  Shinji Fujieda ,  Akio Toda

发明人： Noriaki Kodama ,  Kohji Kanamori ,  Junichi Suzuki ,  Teiichirou Nishizaka ,  Yasuhide Den ,  Shinji Fujieda ,  Akio Toda

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/1033 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7881

摘要： A nonvolatile memory device includes source and drain regions formed in a semiconductor substrate, and an insulating film formed on a channel region between the source region and the drain region in the semiconductor substrate. The nonvolatile memory device also includes a dielectric film formed above the channel region to store electric charge, and a control gate formed on the dielectric film. Compressive stress in the channel region is equal to or less than 50 MPa.

摘要翻译： 非易失性存储器件包括形成在半导体衬底中的源区和漏区，以及形成在半导体衬底中的源区和漏区之间的沟道区上的绝缘膜。 非易失性存储器件还包括形成在通道区域上方以存储电荷的电介质膜，以及形成在电介质膜上的控制栅极。 通道区域的压缩应力为50MPa以下。

公开(公告)号：US20050218490A1

公开(公告)日：2005-10-06

申请号：US11078447

申请日：2005-03-14

申请人： Kohji Kanamori ,  Teiichirou Nishizaka ,  Noriaki Kodama ,  Isao Katayama ,  Yoshihiro Matsuura ,  Kaoru Ishihara ,  Yasushi Harada ,  Naruaki Minenaga ,  Chihiro Oshita

发明人： Kohji Kanamori ,  Teiichirou Nishizaka ,  Noriaki Kodama ,  Isao Katayama ,  Yoshihiro Matsuura ,  Kaoru Ishihara ,  Yasushi Harada ,  Naruaki Minenaga ,  Chihiro Oshita

IPC分类号： H01L27/10 ,  H01L21/322 ,  H01L21/52 ,  H01L21/58 ,  H01L23/26 ,  H01L23/31 ,  H01L23/58 ,  H01L29/00

CPC分类号： H01L23/26 ,  H01L21/3221 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

摘要翻译： 根据本发明，在半导体芯片的侧表面和底表面上沉积吸气层。 然后将半导体芯片安装在封装的板上，使得在底表面上形成肖特基势垒。 通过这种结构，可以通过沉积在半导体芯片的侧表面和/或底表面上的缺陷层和肖特基势垒捕获穿过封装板的金属离子。

公开(公告)号：US20050199945A1

公开(公告)日：2005-09-15

申请号：US11074064

申请日：2005-03-08

申请人： Noriaki Kodama ,  Kohji Kanamori ,  Junichi Suzuki ,  Teiichirou Nishizaka ,  Yasuhide Den ,  Shinji Fujieda ,  Akio Toda

发明人： Noriaki Kodama ,  Kohji Kanamori ,  Junichi Suzuki ,  Teiichirou Nishizaka ,  Yasuhide Den ,  Shinji Fujieda ,  Akio Toda

IPC分类号： H01L21/8247 ,  H01L21/8239 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L29/10 ,  H01L29/745 ,  H01L29/76 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/1033 ,  H01L29/7845 ,  H01L29/7846 ,  H01L29/7881

摘要： A nonvolatile memory device includes source and drain regions formed in a semiconductor substrate, and an insulating film formed on a channel region between the source region and the drain region in the semiconductor substrate. The nonvolatile memory device also includes a dielectric film formed above the channel region to store electric charge, and a control gate formed on the dielectric film. Compressive stress in the channel region is equal to or less than 50 MPa.

摘要翻译： 非易失性存储器件包括形成在半导体衬底中的源区和漏区，以及形成在半导体衬底中的源区和漏区之间的沟道区上的绝缘膜。 非易失性存储器件还包括形成在通道区域上方以存储电荷的电介质膜，以及形成在电介质膜上的控制栅极。 通道区域的压缩应力为50MPa以下。

公开(公告)号：US20050029577A1

公开(公告)日：2005-02-10

申请号：US10892553

申请日：2004-07-16

申请人： Teiichirou Nishizaka ,  Kohji Kanamori

发明人： Teiichirou Nishizaka ,  Kohji Kanamori

IPC分类号： G11C16/04 ,  H01L21/28 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/336 ,  H01L29/94

CPC分类号： H01L27/11568 ,  G11C16/0458 ,  G11C16/0491 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/7923

摘要： A semiconductor memory device comprises diffusion regions, a floating gate, a third diffusion region, a selection gate electrode, and a control gate electrode that three-dimensionally crosses the selection gate electrode and extends in a direction orthogonal to the selection gate electrode are included. A channel formed immediately below the selection gate and which constitutes a passage connecting the two diffusion regions has a shape in a top view, including a first path extending in one direction, from one diffusion region, and a second path extending from the end of the first path to the other diffusion region in a direction orthogonal to a first direction.

摘要翻译： 包括半导体存储器件，其包括扩散区域，浮置栅极，第三扩散区域，选择栅极电极和三维地穿过选择栅电极并沿与选择栅电极正交的方向延伸的控制栅电极。 形成在选择栅极正下方的通道，其构成连接两个扩散区域的通道，具有从一个扩散区域向一个扩散区域延伸的包括从一个方向延伸的第一路径和从第二路径延伸的第二路径的俯视图形状 在与第一方向正交的方向上的另一扩散区的第一路径。

公开(公告)号：US07327019B2

公开(公告)日：2008-02-05

申请号：US11078447

申请日：2005-03-14

申请人： Kohji Kanamori ,  Teiichirou Nishizaka ,  Noriaki Kodama ,  Isao Katayama ,  Yoshihiro Matsuura ,  Kaoru Ishihara ,  Yasushi Harada ,  Naruaki Minenaga ,  Chihiro Oshita

发明人： Kohji Kanamori ,  Teiichirou Nishizaka ,  Noriaki Kodama ,  Isao Katayama ,  Yoshihiro Matsuura ,  Kaoru Ishihara ,  Yasushi Harada ,  Naruaki Minenaga ,  Chihiro Oshita

IPC分类号： H01L23/20 ,  H01L23/02 ,  H01L23/053 ,  H01L23/12 ,  H01L23/14

CPC分类号： H01L23/26 ,  H01L21/3221 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

摘要翻译： 根据本发明，在半导体芯片的侧表面和底表面上沉积吸气层。 然后将半导体芯片安装在封装的板上，使得在底表面上形成肖特基势垒。 通过这种结构，可以通过沉积在半导体芯片的侧表面和/或底表面上的缺陷层和肖特基势垒捕获穿过封装板的金属离子。

公开(公告)号：US20060180891A1

公开(公告)日：2006-08-17

申请号：US11398534

申请日：2006-04-06

申请人： Kohji Kanamori ,  Teiichirou Nishizaka ,  Noriaki Kodama ,  Isao Katayama ,  Yoshihiro Matsuura ,  Kaoru Ishihara ,  Yasushi Harada ,  Naruaki Minenaga ,  Chihiro Oshita

发明人： Kohji Kanamori ,  Teiichirou Nishizaka ,  Noriaki Kodama ,  Isao Katayama ,  Yoshihiro Matsuura ,  Kaoru Ishihara ,  Yasushi Harada ,  Naruaki Minenaga ,  Chihiro Oshita

IPC分类号： H01L31/07 ,  H01L27/095 ,  H01L31/108 ,  H01L29/47 ,  H01L29/812

CPC分类号： H01L23/26 ,  H01L21/3221 ,  H01L23/3128 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： According to the present invention, a gettering layer is deposited both on the side surfaces and the bottom surface of a semiconductor chip. The semiconductor chip is then mounted on the board of a package so that a Schottky barrier is formed on the bottom surface. With this structure, metal ions that pass through the board of the package can be captured by the defect layer deposited on the side surfaces and/or the bottom surface of the semiconductor chip, and by the Schottky barrier.

摘要翻译： 根据本发明，在半导体芯片的侧表面和底表面上沉积吸气层。 然后将半导体芯片安装在封装的板上，使得在底表面上形成肖特基势垒。 通过这种结构，可以通过沉积在半导体芯片的侧表面和/或底表面上的缺陷层和肖特基势垒捕获穿过封装板的金属离子。

公开(公告)号：US5721701A

公开(公告)日：1998-02-24

申请号：US639753

申请日：1996-04-29

申请人： Masazumi Ikebe ,  Teiichirou Nishizaka

发明人： Masazumi Ikebe ,  Teiichirou Nishizaka

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C11/34

CPC分类号： G11C11/5692 ,  G11C11/56 ,  G11C16/08 ,  G11C2211/5632 ,  G11C8/00

摘要： In a multivalued ROM device including a plurality of memory cells each for storing N (N=2, 3, . . . )-bit information, each bit of the N-bit information corresponds to one address.

摘要翻译： 在包含多个用于存储N（N = 2,3，...）位信息的多个存储单元的多值ROM装置中，N位信息的每个位对应于一个地址。