公开(公告)号：US07782700B2

公开(公告)日：2010-08-24

申请号：US12420275

申请日：2009-04-08

申请人： Kenichi Kuboyama ,  Hideaki Arima

发明人： Kenichi Kuboyama ,  Hideaki Arima

IPC分类号： G11C7/00 ,  G11C5/14

CPC分类号： G11C29/02 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/109 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/2254

摘要： In a semiconductor or memory device, a first ODT (On Die Termination) circuit is provided between a termination voltage port and a command input port. A first ODT controlling circuit is connected between the termination voltage port and the first ODT circuit, and detects a level of a voltage applied to the termination voltage port and controls the first ODT circuit to connect the termination voltage port and the command input port based on the detection result.

摘要翻译： 在半导体或存储器件中，在终端电压端口和命令输入端口之间提供第一ODT（On Die Termination）电路。 第一ODT控制电路连接在终端电压端口和第一ODT电路之间，并且检测施加到终端电压端口的电压的电平，并且控制第一ODT电路以连接端接电压端口和命令输入端口，基于 检测结果。

公开(公告)号：US20070183222A1

公开(公告)日：2007-08-09

申请号：US11700186

申请日：2007-01-31

申请人： Kohji Kanamori ,  Kenichi Kuboyama

发明人： Kohji Kanamori ,  Kenichi Kuboyama

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： H01L27/115 ,  G11C16/10

摘要： A programmable non-volatile semiconductor memory device includes a select gate 3, arranged in a first region on a substrate, a floating gate 6 arranged in a second region neighboring to the first region, a first diffusion region 7 provided in a third region neighboring to the second region, a control gate 11 arranged on the floating gate 6, and a driving circuit 22 adapted for controlling voltages applied to the substrate 1 (well 1a), select gate 3, first diffusion region 7 and control gate 11. The driving circuit performs control so that, during erasure operation, voltages applied to select gate 3 and the control gate 11 are negative, with the remaining voltage, applied to the substrate 1 (or well 1a), being positive. The device permits erasure operation at a lower voltage.

摘要翻译： 可编程非易失性半导体存储器件包括：布置在衬底上的第一区域中的选择栅极3，布置在与第一区域相邻的第二区域中的浮置栅极6，设置在与第一区域相邻的第三区域中的第一扩散区域7 第二区域，布置在浮置栅极6上的控制栅极11和适于控制施加到基板1（阱1a），选择栅极3，第一扩散区域7和控制栅极11的电压的驱动电路22。 电路进行控制，使得在擦除操作期间，施加到选择栅极3和控制栅极11的电压为负，而施加到衬底1（或阱1a）的剩余电压为正。 该器件允许在较低电压下的擦除操作。

公开(公告)号：US20090256587A1

公开(公告)日：2009-10-15

申请号：US12420275

申请日：2009-04-08

申请人： Kenichi Kuboyama ,  Hideaki Arima

发明人： Kenichi Kuboyama ,  Hideaki Arima

IPC分类号： H03K19/003

CPC分类号： G11C29/02 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/109 ,  G11C29/025 ,  G11C29/028 ,  G11C29/50008 ,  G11C2207/2254

摘要： In a semiconductor memory device, a first ODT (On Die Termination) circuit is provided between a termination voltage port and a command input port. A first ODT controlling circuit is connected between the termination voltage port and controls the first ODT circuit to connect the termination voltage port and the command input port based on the detection result.

摘要翻译： 在半导体存储器件中，在终端电压端口和命令输入端口之间提供第一ODT（On Die Termination）电路。 第一个ODT控制电路连接在终端电压端口之间，并根据检测结果控制第一个ODT电路，以连接终端电压端口和命令输入端口。

公开(公告)号：US20060244040A1

公开(公告)日：2006-11-02

申请号：US11410091

申请日：2006-04-25

申请人： Kenichi Kuboyama ,  Kohji Kanamori

发明人： Kenichi Kuboyama ,  Kohji Kanamori

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/7885

摘要： A semiconductor-memory device that reduces leak off due to miniaturization of memory cells, and comprises as a single unit cell: a substrate 1 having a trench section 1a; a selector gate 3 that is located via an insulating film 2 on the substrate adjacent to the trench section 1a; a first well 1b that is formed on the surface of the substrate 1 below the selector gate 3; a floating gate 6 that is located via an insulating film 8a on the surface of the bottom section and sidewall section of the trench section 1a; a second well 1c that is formed on the surface of the bottom section of the trench section 1a below the floating gate 6; a first diffusion area 7a that is formed on the surface of the bottom section of the trench section 1a; and a control gate 11 located via an insulating film 8 on top of the floating gate 6; and where the area near the sidewall surface and bottom surface of the trench section 1a forms a channel in the selector gate 3; and the impurity density of the first well 1b is not more than the impurity density of the second well 1c.

摘要翻译： 一种半导体存储器件，其减小由于存储单元的小型化引起的泄漏，并且包括作为单个单元电池：具有沟槽部分1a的衬底1; 选择栅3，其经由与沟槽部1a相邻的基板上的绝缘膜2定位; 形成在选择栅3下方的基板1的表面上的第一阱1b; 位于沟槽部分1a的底部表面和侧壁部分的绝缘膜8a上的浮动栅极6; 形成在浮动栅极6下方的沟槽部分1a的底部表面上的第二阱1c; 形成在沟槽部1a的底部的表面上的第一扩散区域7a; 以及通过绝缘膜8位于浮动栅极6的顶部上的控制栅极11; 并且其中沟槽部分1a的侧壁表面和底表面附近的区域在选择器门3中形成通道; 并且第一阱1b的杂质浓度不大于第二阱1c的杂质浓度。

公开(公告)号：US08760943B2

公开(公告)日：2014-06-24

申请号：US13599730

申请日：2012-08-30

申请人： Toshihiko Funaki ,  Toshiharu Okamoto ,  Muneaki Matsushige ,  Kenichi Kuboyama ,  Shuuichi Senou ,  Susumu Takano

发明人： Toshihiko Funaki ,  Toshiharu Okamoto ,  Muneaki Matsushige ,  Kenichi Kuboyama ,  Shuuichi Senou ,  Susumu Takano

IPC分类号： G11C7/00 ,  G11C7/10 ,  G11C8/00 ,  G11C8/06 ,  G11C8/12 ,  G11C11/4096

CPC分类号： G11C7/1048 ,  G11C7/00 ,  G11C7/10 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/4096 ,  H03K5/15006

摘要： A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.

摘要翻译： 根据本发明的一个方面的半导体装置包括第一和第二总线接口电路，通过第一数据总线连接到第一总线接口电路的第一存储器核心，第一存储器核心连接到第一存取控制信号 从第一总线接口电路输出的第二存储器核心，通过第二数据总线连接到第二总线接口电路的第二存储器核心，以及选择性地将第一存取控制信号和第二存取控制信号输出的第二存取控制信号 第二总线接口电路到第二存储器核心。

公开(公告)号：US07619278B2

公开(公告)日：2009-11-17

申请号：US11410091

申请日：2006-04-25

申请人： Kenichi Kuboyama ,  Kohji Kanamori

发明人： Kenichi Kuboyama ,  Kohji Kanamori

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  G11C16/0433 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/7885

摘要： A semiconductor-memory device that reduces leak off due to miniaturization of memory cells, and comprises as a single unit cell: a substrate 1 having a trench section 1a; a selector gate 3 that is located via an insulating film 2 on the substrate adjacent to the trench section 1a; a first well 1b that is formed on the surface of the substrate 1 below the selector gate 3; a floating gate 6 that is located via an insulating film 8a on the surface of the bottom section and sidewall section of the trench section 1a; a second well 1c that is formed on the surface of the bottom section of the trench section 1a below the floating gate 6; a first diffusion area 7a that is formed on the surface of the bottom section of the trench section 1a; and a control gate 11 located via an insulating film 8 on top of the floating gate 6; and where the area near the sidewall surface and bottom surface of the trench section 1a forms a channel in the selector gate 3; and the impurity density of the first well 1b is not more than the impurity density of the second well 1c.

摘要翻译： 一种半导体存储器件，其减少由于存储单元的小型化而导致的泄漏，并且包括作为单个单元电池：具有沟槽部分1a的衬底1; 选择栅3，其经由与沟槽部1a相邻的基板上的绝缘膜2定位; 形成在选择栅3下方的基板1的表面上的第一阱1b; 位于沟槽部分1a的底部表面和侧壁部分的绝缘膜8a上的浮动栅极6; 形成在浮动栅极6下方的沟槽部分1a的底部表面上的第二阱1c; 在沟槽部分1a的底部表面上形成的第一扩散区域7a; 以及通过绝缘膜8位于浮动栅极6的顶部上的控制栅极11; 并且其中沟槽部分1a的侧壁表面和底表面附近的区域在选择器门3中形成通道; 并且第一阱1b的杂质浓度不大于第二阱1c的杂质浓度。

公开(公告)号：US07580293B2

公开(公告)日：2009-08-25

申请号：US11700186

申请日：2007-01-31

申请人： Kohji Kanamori ,  Kenichi Kuboyama

发明人： Kohji Kanamori ,  Kenichi Kuboyama

IPC分类号： G11C16/04

CPC分类号： H01L27/115 ,  G11C16/10

摘要： A programmable non-volatile semiconductor memory device includes a select gate 3, arranged in a first region on a substrate, a floating gate 6 arranged in a second region neighboring to the first region, a first diffusion region 7 provided in a third region neighboring to the second region, a control gate 11 arranged on the floating gate 6, and a driving circuit 22 adapted for controlling voltages applied to the substrate 1 (well 1a), select gate 3, first diffusion region 7 and control gate 11. The driving circuit performs control so that, during erasure operation, voltages applied to select gate 3 and the control gate 11 are negative, with the remaining voltage, applied to the substrate 1 (or well 1a), being positive. The device permits erasure operation at a lower voltage.

摘要翻译： 可编程非易失性半导体存储器件包括：布置在衬底上的第一区域中的选择栅极3，布置在与第一区域相邻的第二区域中的浮置栅极6，设置在与第一区域相邻的第三区域中的第一扩散区域7 第二区域，布置在浮置栅极6上的控制栅极11和适于控制施加到基板1（阱1a），选择栅极3，第一扩散区域7和控制栅极11的电压的驱动电路22。 执行控制，使得在擦除操作期间，施加到选择栅极3和控制栅极11的电压为负，而施加到衬底1（或阱1a）的剩余电压为正。 该器件允许在较低电压下的擦除操作。

公开(公告)号：US20130051110A1

公开(公告)日：2013-02-28

申请号：US13599730

申请日：2012-08-30

申请人： Toshihiko FUNAKI ,  Toshiharu OKAMOTO ,  Muneaki MATSUSHIGE ,  Kenichi KUBOYAMA ,  Shuuichi SENOU ,  Susumu TAKANO

发明人： Toshihiko FUNAKI ,  Toshiharu OKAMOTO ,  Muneaki MATSUSHIGE ,  Kenichi KUBOYAMA ,  Shuuichi SENOU ,  Susumu TAKANO

IPC分类号： G11C5/06

CPC分类号： G11C7/1048 ,  G11C7/00 ,  G11C7/10 ,  G11C7/1006 ,  G11C8/12 ,  G11C11/4096 ,  H03K5/15006

摘要： A semiconductor apparatus according to an aspect of the present invention includes first and second bus-interface circuits, a first memory core connected to the first bus-interface circuit through a first data bus, the first memory core being connected to a first access control signal output from the first bus-interface circuit, a second memory core connected to the second bus-interface circuit through a second data bus, and a select circuit that selectively connects one of the first access control signal and a second access control signal output from the second bus-interface circuit to the second memory core.

摘要翻译： 根据本发明的一个方面的半导体装置包括第一和第二总线接口电路，通过第一数据总线连接到第一总线接口电路的第一存储器核心，第一存储器核心连接到第一存取控制信号 从第一总线接口电路输出的第二存储器核心，通过第二数据总线连接到第二总线接口电路的第二存储器核心，以及选择性地将第一存取控制信号和第二存取控制信号输出的第二存取控制信号 第二总线接口电路到第二存储器核心。