A programmable non-volatile semiconductor memory device having which a sufficient operational margin with miniaturized memory cells. The memory device includes select gates 3, arranged in a first region on a substrate 1, floating gates 6, arranged in a second region, neighboring to the first region, first diffusion regions 7, arranged in a third region neighboring to the second region, and control gates 11 arranged above the floating gates 6. It also includes a driving circuit 22 for controlling the voltages applied to the substrate 1, select gates 3, first diffusion areas 7 and the controlling gates 11. At the time of reprogramming, the driving circuit 22 controls the voltages for first control and second control. The first control sets a low threshold voltage state, inclusive of the depletion state, for the bits, connected to a selected one of the control gates 11. The second control sets a low threshold voltage state or a high threshold voltage state of a desired enhancement state from one bit to another.