公开(公告)号：US09276041B2

公开(公告)日：2016-03-01

申请号：US13423793

申请日：2012-03-19

Applicant: Eng Huat Toh ,  Elgin Quek ,  Shyue Seng Tan

Inventor： Eng Huat Toh ,  Elgin Quek ,  Shyue Seng Tan

IPC: H01L47/00 ,  H01L27/24 ,  H01L45/00

CPC classification number: H01L27/2409 ,  H01L27/2445 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1675

Abstract: Disclosed herein are various embodiments of novel three dimensional RRAM devices, and various methods of making such devices. In one example, a device disclosed herein includes a first electrode for a first bit line comprising a variable resistance material, a second electrode for a second bit line comprising a variable resistance material and a third electrode positioned between the variable resistance material of the first bit line and the variable resistance material of the second bit line.

Abstract translation: 本文公开了新型三维RRAM设备的各种实施例以及制造这些设备的各种方法。 在一个示例中，本文公开的装置包括用于第一位线的第一电极，其包括可变电阻材料，用于第二位线的第二电极，包括可变电阻材料和位于第一位的可变电阻材料之间的第三电极 线和第二位线的可变电阻材料。

公开(公告)号：US09263132B2

公开(公告)日：2016-02-16

申请号：US13206780

申请日：2011-08-10

Applicant: Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek

Inventor： Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek

IPC: H01L21/336 ,  G11C16/04 ,  H01L21/28 ,  H01L29/423 ,  H01L29/66 ,  H01L29/788 ,  H01L27/115

CPC classification number: H01L27/11521 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/14 ,  G11C16/26 ,  H01L21/28273 ,  H01L29/42328 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/7851 ,  H01L29/7881

Abstract: A split gate memory cell is fabricated with a fin structure between a memory gate stack and a select gate. Embodiments include a first channel region under the memory gate stack and a second channel region under the select gate.

Abstract translation: 在存储器栅极堆叠和选择栅极之间制造具有鳍结构的分离栅极存储器单元。 实施例包括存储器栅极堆叠下方的第一沟道区域和选择栅极下方的第二沟道区域。

公开(公告)号：US09252270B2

公开(公告)日：2016-02-02

申请号：US13713393

申请日：2012-12-13

Applicant: Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek

Inventor： Shyue Seng Tan ,  Eng Huat Toh ,  Elgin Quek

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7841 ,  H01L29/66545 ,  H01L29/78654

Abstract: Methods of forming a floating body cell (FBC) with faster programming and lower refresh rate and the resulting devices are disclosed. Embodiments include forming a silicon on insulator (SOI) layer on a substrate; forming a band-engineered layer surrounding and/or on the SOI layer; forming a source region and a drain region with at least one of the source region and the drain region being on the band-engineered layer; and forming a gate on the SOI layer, between the source and drain regions.

Abstract translation: 公开了具有更快编程和更低刷新率的浮体单元（FBC）的形成方法以及所得到的器件。 实施例包括在基板上形成绝缘体上硅（SOI）层; 形成围绕和/或在SOI层上的带工程层; 形成源极区域和漏极区域，所述源极区域和漏极区域中的至少一个在所述带状工程化层上; 以及在SOI层上，在源区和漏区之间形成栅极。

公开(公告)号：US08895402B2

公开(公告)日：2014-11-25

申请号：US13602310

申请日：2012-09-03

Applicant: Eng Huat Toh ,  Elgin Quek ,  Shyue Seng Tan

Inventor： Eng Huat Toh ,  Elgin Quek ,  Shyue Seng Tan

IPC: H01L21/20

CPC classification number: H01L45/1233 ,  H01L45/04 ,  H01L45/06 ,  H01L45/126 ,  H01L45/141 ,  H01L45/144 ,  H01L45/146 ,  H01L45/1675 ,  H01L45/1691

Abstract: Memory devices and methods for forming a device are disclosed. A substrate prepared with a lower electrode level with bottom electrodes is provided. Fin stack layers are formed on the lower electrode level. Spacers are formed on top of the fin stack layers. The spacers have a width which is less than a lithographic resolution. The fin stack layers are patterned using the spacers as a mask to form fin stacks. The fin stacks contact the bottom electrodes. An interlevel dielectric (ILD) layer is formed on the substrate. The ILD layer fills spaces around the fin stacks. An upper electrode level is formed on the ILD layer. The upper electrode level has top electrodes in contact with the fin stacks. The electrodes and fin stacks form fin-type memory cells.

Abstract translation: 公开了用于形成装置的存储装置和方法。 提供了制备具有与底部电极的较低电极电平的衬底。 鳍状堆叠层形成在下部电极层上。 垫片形成在翅片堆叠层的顶部。 间隔物的宽度小于光刻分辨率。 使用间隔件作为掩模来对翅片堆叠层进行图案化以形成翅片堆叠。 鳍片堆叠接触底部电极。 在衬底上形成层间电介质（ILD）层。 ILD层填充散热片堆叠周围的空间。 在ILD层上形成上电极层。 上电极电平具有与散热片堆叠接触的顶部电极。 电极和散热片堆叠形成鳍式存储单元。

公开(公告)号：US08748271B2

公开(公告)日：2014-06-10

申请号：US13046313

申请日：2011-03-11

Applicant: Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

Inventor： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

IPC: H01L29/772 ,  H01L29/40 ,  H01L29/49 ,  H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/495 ,  H01L29/4983 ,  H01L29/512 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/66681

Abstract: An LDMOS is formed with a field plate over the n− drift region, coplanar with the gate stack, and having a higher work function than the gate stack. Embodiments include forming a first conductivity type well, having a source, surrounded by a second conductivity type well, having a drain, in a substrate, forming first and second coplanar gate stacks on the substrate over a portion of the first well and a portion of the second well, respectively, and tuning the work functions of the first and second gate stacks to obtain a higher work function for the second gate stack. Other embodiments include forming the first gate stack of a high-k metal gate and the second gate stack of a field plate on a gate oxide layer, forming the first and second gate stacks with different gate electrode materials on a common gate oxide, and forming the gate stacks separated from each other and with different gate dielectric materials.

Abstract translation: LDMOS在n-漂移区上形成有与栅叠层共面的场板，并且具有比栅叠层更高的功函数。 实施例包括形成第一导电类型的阱，具有由第二导电类型阱包围的源，在衬底中具有漏极，在衬底上在第一阱的一部分上形成第一和第二共面栅叠层， 分别调整第一和第二栅极堆叠的功函数，以获得第二栅极堆叠的较高功函数。 其他实施例包括在栅极氧化物层上形成高k金属栅极的第一栅极堆叠和场板的第二栅极堆叠，在公共栅极氧化物上形成具有不同栅电极材料的第一和第二栅极堆叠，以及形成 栅极堆叠彼此分离并具有不同的栅极电介质材料。

公开(公告)号：US08492235B2

公开(公告)日：2013-07-23

申请号：US12980375

申请日：2010-12-29

Applicant: Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

Inventor： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Elgin Quek

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1037 ,  H01L29/1054 ,  H01L29/41783 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849

Abstract: A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduced height variations across the wafer. The fin type transistor may also include a buried stressor and/or raised or embedded raised S/D stressors to cause a strain in the channel to improve carrier mobility.

公开(公告)号：US20120223394A1

公开(公告)日：2012-09-06

申请号：US13041134

申请日：2011-03-04

Applicant: Eng Huat Toh ,  Elgin Quek

Inventor： Eng Huat Toh ,  Elgin Quek

IPC: H01L27/088 ,  H01L21/28

CPC classification number: H01L27/088 ,  H01L21/28518 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823475 ,  H01L29/78

Abstract: A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches.

Abstract translation: 高K /金属栅极半导体器件具有较大的自对准触点，电阻降低。 实施例包括在源极/漏极区域之间的衬底上形成第一高k金属栅极堆叠，在STI区域上形成第二高k金属栅极堆叠以及在金属栅极堆叠之间形成第一ILD，形成蚀刻停止层和 在衬底上顺序地具有第二ILD，在金属栅堆叠上的第二ILD中具有开口，在开口的边缘上形成间隔物，在第二ILD和间隔物上形成第三ILD，在源/漏区上去除第一ILD 在邻近间隔物的源极/漏极区域上以及在间隔物的一部分上方去除蚀刻停止层，第二ILD和第三ILD，形成第一沟槽，在第二高k金属栅极上去除第三ILD 堆叠和一部分间隔物，形成第二沟槽，并在第一和第二沟槽中形成接触。

公开(公告)号：US20120038009A1

公开(公告)日：2012-02-16

申请号：US12806354

申请日：2010-08-11

Applicant: Eng Huat Toh ,  Elgin Quek ,  Chunshan Yin ,  Chung Foong Tan ,  Jae Gon Lee

Inventor： Eng Huat Toh ,  Elgin Quek ,  Chunshan Yin ,  Chung Foong Tan ,  Jae Gon Lee

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/28079 ,  H01L21/28088 ,  H01L21/28097 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/517

Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff.

Abstract translation: 制造半导体器件的方法（和半导体器件）提供具有降低的栅极接触电阻（和串联电阻）的场效应晶体管（FET），以提高器件性能。 在金属栅极电极和栅极接触层之间的杂质区域中将杂质注入或沉积在栅极堆叠中。 执行退火处理，其将杂质区域转换成偏析层，其降低金属栅电极（例如，硅化物）和栅极接触层（例如非晶硅）之间的界面的肖特基势垒高度（SBH）。 这导致较低的栅极接触电阻并有效降低器件的AC Reff。

公开(公告)号：US20120018815A1

公开(公告)日：2012-01-26

申请号：US12804487

申请日：2010-07-22

Applicant: Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Shiang Yang Ong ,  Elgin Quek

Inventor： Eng Huat Toh ,  Jae Gon Lee ,  Chung Foong Tan ,  Shiang Yang Ong ,  Elgin Quek

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7833 ,  H01L21/26506 ,  H01L21/28556 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/66575

Abstract: A method (and semiconductor device) of fabricating a semiconductor device provides a filed effect transistor (FET) with reduced contact resistance (and series resistance) for improved device performance. An impurity is implanted in the source/drain (S/D) regions after contact silicide formation and a spike anneal process is performed that lowers the schottky barrier height (SBH) of the interface between the silicide and the lower junction region of the S/D regions. This results in lower contact resistance and reduces the thickness (and Rs) of the region at the silicide-semiconductor interface.

Abstract translation: 制造半导体器件的方法（和半导体器件）提供具有降低的接触电阻（和串联电阻）的场效应晶体管（FET），以提高器件性能。 在接触硅化物形成之后，在源极/漏极（S / D）区域中注入杂质，并且进行尖峰退火处理，其降低硅化物和S / D层的下部结区之间的界面的肖特基势垒高度（SBH） D区。 这导致较低的接触电阻并且减小了硅化物半导体界面处的区域的厚度（和Rs）。

公开(公告)号：US09362274B2

公开(公告)日：2016-06-07

申请号：US13867684

申请日：2013-04-22

Applicant: Eng Huat Toh ,  Elgin Quek

Inventor： Eng Huat Toh ,  Elgin Quek

IPC: H01L29/76 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/285 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/28518 ,  H01L21/76801 ,  H01L21/76816 ,  H01L21/76834 ,  H01L21/76897 ,  H01L21/823475 ,  H01L29/78

Abstract: A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches.