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    Transistor gain cell with feedback
    2.
    发明授权
    Transistor gain cell with feedback 有权

    公开(公告)号：US09691445B2

    公开(公告)日：2017-06-27

    申请号：US15306796

    申请日：2015-04-30

    Applicant: Bar-Ilan University

    Inventor： Robert Giterman ,  Adam Teman ,  Pascal Meinerzhagen ,  Andreas Burg ,  Alexander Fish

    IPC: G11C5/06 ,  G11C7/10 ,  G11C11/4097 ,  G11C11/412 ,  G11C5/02 ,  H01L27/11

    CPC classification number: G11C7/10 ,  G11C5/025 ,  G11C5/06 ,  G11C11/403 ,  G11C11/4097 ,  G11C11/412 ,  H01L27/11 ,  H01L27/1104

    Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The gain cell also includes a write transistor, retention element and read transistor. Each of the transistors includes a respective first diffusion connection, gate connection and second diffusion connection. The write transistor first diffusion connection is connected to the write bit line input and the write transistor gate connection is connected to the write trigger input. The read transistor first diffusion connection being connected to the read bit line output and the second diffusion connection is connected to the read trigger input. The retention element buffers between write transistor and the read transistor during data retention. The retention element also connects or disconnects a write transistor diffusion connection to/from a constant voltage in accordance with a retained data level at the read transistor gate connection.

    Data-dependent delay circuits
    3.
    发明授权
    Data-dependent delay circuits 有权

    公开(公告)号：US10521530B2

    公开(公告)日：2019-12-31

    申请号：US15636902

    申请日：2017-06-29

    Applicant: Bar-Ilan University

    Inventor： Itamar Levi ,  Osnat Keren ,  Alexander Fish

    IPC: G06F17/50 ,  H03K5/135 ,  H03L7/081 ,  G06F1/10

    Abstract: A method of designing a logic circuit with data-dependent delays is performed using an electronic design automation system. The logic circuit includes logic paths from logic inputs to at least one logic output. The method includes: obtaining an initial circuit design; specifying respective delays for multiple logic paths in the initial circuit design such that at least some of the outputs switch at different times within a clock cycle for different combinations of logic input levels; and forming a second circuit design having the specified respective delays along the respective logic paths by adding delay elements to the initial circuit design based on the specified respective delays.

    High-density memory macro
    4.
    发明申请
    High-density memory macro 审中-公开

    公开(公告)号：US20190074040A1

    公开(公告)日：2019-03-07

    申请号：US16121672

    申请日：2018-09-05

    Applicant: Mellanox Technologies, Ltd. ,  Bar-Ilan University

    Inventor： Elad Mentovich ,  Narkis Geuli ,  Robert Giterman ,  Alexander Fish ,  Adam Teman

    IPC: G11C7/10 ,  G11C11/403 ,  G11C11/4097 ,  G11C11/412

    Abstract: A high-density memory includes: a data write interface, a data read interface, an array of memory cells and level-shifting write drivers. The data write interface inputs data written to the memory. The data read interface outputs data read from the memory. The array of memory cells stores data input at the data write interface and outputs stored data to the data read interface. Each of the memory cells includes at least one low threshold voltage (LVT) read transistor and at least one respective regular threshold voltage (RVT) transistor, so as to obtain high-speed read operations. The level-shifting write drivers supply shifted write wordline voltages to the array, so as to obtain high-speed write operations.

    INTEGRATED CIRCUIT WITH PHOTONIC ELEMENTS
    5.
    发明申请
    INTEGRATED CIRCUIT WITH PHOTONIC ELEMENTS 审中-公开
    集成电路与光电元件

    公开(公告)号：US20150253502A1

    公开(公告)日：2015-09-10

    申请号：US14427756

    申请日：2013-09-11

    Applicant: Ben-Gurion University of the Negev Research and Development Authority ,  Bar-Ilan University

    Inventor： Alexander Fish ,  Zeev Zalevsky ,  Amihai Meiri ,  Ori Bass

    IPC: G02B6/122

    CPC classification number: G02B6/1225 ,  B82Y20/00 ,  G02B6/12004 ,  G02B6/12007 ,  G02B6/122 ,  G06E3/005

    Abstract: An integrated circuit with electronic and photonic elements includes: at least one electronic processing layer; at least one interconnect layer adjacent to said electronic processing layer, and at least one photonic element located within a respective interconnect layer. The photonic elements implement respective operations upon optical signals. At least a portion of each interconnect layer which includes photonic elements is optically-conductive, and therefore suitable for the inclusion of the photonic elements.In some embodiments said photonic elements comprising optical waveguides are configures as optical logic gates to perform logic operations.

    Abstract translation: 具有电子和光子元件的集成电路包括：至少一个电子处理层; 与所述电子处理层相邻的至少一个互连层和位于相应互连层内的至少一个光子元件。 光子元件根据光信号实现各自的操作。 包括光子元件的每个互连层的至少一部分是光学导电的，因此适合于包含光子元件。 在一些实施例中，包括光波导的所述光子元件被配置为执行逻辑运算的光逻辑门。

    Fin-FET gain cells
    6.
    发明授权
    Fin-FET gain cells 有权

    公开(公告)号：US11127455B2

    公开(公告)日：2021-09-21

    申请号：US16699003

    申请日：2019-11-28

    Applicant: Bar-Ilan University

    Inventor： Adam Teman ,  Amir Shalom ,  Robert Giterman ,  Alexander Fish

    IPC: G11C11/4096 ,  H01L27/108 ,  H01L23/528 ,  H01L27/02 ,  H01L29/78

    Abstract: A FinFET gain cell includes a write port, read port and storage node. The write port includes at least one write FinFET transistor and has write word-line (WWL) and write bit-line (WBL) inputs. The read port includes at least one FinFET read transistor and has a read word-line (RWL) input and a read bit-line (RBL) output. The storage node stores a data level written from said WBL. The storage nodes includes a single layer interconnect which connects the write port output diffusion connection to the read port input gate connection. The height of the single layer interconnect at the write port output diffusion connection is different from the height of the single layer interconnect at the read port input gate connection.

    Randomized logic against side channel attacks
    10.
    发明授权
    Randomized logic against side channel attacks 有权

    公开(公告)号：US10951391B2

    公开(公告)日：2021-03-16

    申请号：US15757658

    申请日：2016-09-06

    Applicant: Bar-Ilan University

    Inventor： Moshe Avital ,  Itamar Levy ,  Osnat Keren ,  Alexander Fish

    IPC: G06F11/30 ,  G06F12/14 ,  H04L9/00 ,  G06F21/72 ,  G09C1/00 ,  G06F21/75

    Abstract: A randomization element includes a logic input for inputting a logic signal, a logic output for outputting the input logic signal at a delay and a randomization element. The randomization elements introduces the delay between said logic input and said logic output and operates selectably in static mode and in dynamic mode in accordance with a mode control signal. A logic circuit may be formed with randomization elements interspersed amongst the logic gates, to obtain protection against side channel attacks by inputting a selected control sequence into the randomization elements.

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