公开(公告)号：US20190074984A1

公开(公告)日：2019-03-07

申请号：US15694809

申请日：2017-09-03

Applicant: BAR-ILAN UNIVERSITY

Inventor： Joseph Shor ,  Yoav Weizman ,  Yitzhak Schifmann

IPC: H04L9/32 ,  G11C11/412 ,  G11C11/417

Abstract: A method for detecting unreliable bits in transistor circuitry includes applying a controllable physical parameter to a transistor circuitry, thereby causing a variation in a digital code of a cryptologic element in the transistor circuitry, the variation being a tilt or bias in a positive or negative direction. An amount of variation in the digital code of the cryptologic element is determined. Unreliable bits in the transistor circuitry are defined as those bits for which the variation is in a range defined as unreliable.

公开(公告)号：US20220166431A1

公开(公告)日：2022-05-26

申请号：US17529456

申请日：2021-11-18

Applicant: Bar Ilan University

Inventor： Joseph Shor ,  Yitzhak Schifmann ,  Inbal Stanger ,  Netanel Shavit ,  Edison Ramiro Taco Lasso ,  Alexander Fish

IPC: H03K19/003 ,  G06F1/30 ,  G01R19/165

Abstract: A technique to mitigate timing errors induced by power supply droops includes an inverter-based droop detector as well as Dual Mode Logic (DML) to achieve a droop-resist ant timing response. The droop detector is based on capacitor ratios and is thus less sensitive to Process/Voltage/Temperature (PVT) and to random offset than the prior art. The DML can alter its power/performance ratio based on the droop level input it receives from the detector, such that the critical timings are preserved.