公开(公告)号：US10002660B2

公开(公告)日：2018-06-19

申请号：US15632555

申请日：2017-06-26

Applicant: Bar-Ilan University

Inventor： Robert Giterman ,  Adam Teman ,  Pascal Meinerzhagen ,  Andreas Burg ,  Alexander Fish

IPC: G11C5/06 ,  G11C11/41 ,  G11C11/403 ,  G11C11/4097 ,  G11C5/02 ,  G11C7/10 ,  H01L27/11 ,  G11C8/14 ,  G11C8/16 ,  G11C11/405

CPC classification number: G11C11/41 ,  G11C5/025 ,  G11C5/063 ,  G11C7/10 ,  G11C8/14 ,  G11C8/16 ,  G11C11/403 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/1104

Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The write element writes a data level from the write bit line input to the gain cell when triggered by the write trigger input. The retention element buffers between an internal buffer node and an internal storage node during data retention. The retention element also connects or disconnects the buffer node to a first constant voltage according to the data level being retained in the gain cell. The read element decouples the storage node from the read bit line output during data read. The read element also connects and disconnects the read bit line output to a second constant voltage according to the data level being read from the gain cell.

公开(公告)号：US09691445B2

公开(公告)日：2017-06-27

申请号：US15306796

申请日：2015-04-30

Applicant: Bar-Ilan University

Inventor： Robert Giterman ,  Adam Teman ,  Pascal Meinerzhagen ,  Andreas Burg ,  Alexander Fish

IPC: G11C5/06 ,  G11C7/10 ,  G11C11/4097 ,  G11C11/412 ,  G11C5/02 ,  H01L27/11

CPC classification number: G11C7/10 ,  G11C5/025 ,  G11C5/06 ,  G11C11/403 ,  G11C11/4097 ,  G11C11/412 ,  H01L27/11 ,  H01L27/1104

Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The gain cell also includes a write transistor, retention element and read transistor. Each of the transistors includes a respective first diffusion connection, gate connection and second diffusion connection. The write transistor first diffusion connection is connected to the write bit line input and the write transistor gate connection is connected to the write trigger input. The read transistor first diffusion connection being connected to the read bit line output and the second diffusion connection is connected to the read trigger input. The retention element buffers between write transistor and the read transistor during data retention. The retention element also connects or disconnects a write transistor diffusion connection to/from a constant voltage in accordance with a retained data level at the read transistor gate connection.

公开(公告)号：US20170294221A1

公开(公告)日：2017-10-12

申请号：US15632555

申请日：2017-06-26

Applicant: Bar-Ilan University

Inventor： Robert GITERMAN ,  Adam Teman ,  Pascal Meinerzhagen ,  Andreas Burg ,  Alexander Fish

IPC: G11C11/41 ,  G11C11/403 ,  H01L27/11 ,  G11C5/02 ,  G11C7/10 ,  G11C5/06 ,  G11C11/4097

CPC classification number: G11C11/41 ,  G11C5/025 ,  G11C5/063 ,  G11C7/10 ,  G11C8/14 ,  G11C8/16 ,  G11C11/403 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/1104

Abstract: A gain cell includes a write bit line input, a read bit line output, a write trigger input and a read trigger input. The write element writes a data level from the write bit line input to the gain cell when triggered by the write trigger input. The retention element buffers between an internal buffer node and an internal storage node during data retention. The retention element also connects or disconnects the buffer node to a first constant voltage according to the data level being retained in the gain cell. The read element decouples the storage node from the read bit line output during data read. The read element also connects and disconnects the read bit line output to a second constant voltage according to the data level being read from the gain cell.