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    Data-dependent delay circuits
    1.
    发明授权
    Data-dependent delay circuits 有权

    公开(公告)号：US10521530B2

    公开(公告)日：2019-12-31

    申请号：US15636902

    申请日：2017-06-29

    Applicant: Bar-Ilan University

    Inventor： Itamar Levi ,  Osnat Keren ,  Alexander Fish

    IPC: G06F17/50 ,  H03K5/135 ,  H03L7/081 ,  G06F1/10

    Abstract: A method of designing a logic circuit with data-dependent delays is performed using an electronic design automation system. The logic circuit includes logic paths from logic inputs to at least one logic output. The method includes: obtaining an initial circuit design; specifying respective delays for multiple logic paths in the initial circuit design such that at least some of the outputs switch at different times within a clock cycle for different combinations of logic input levels; and forming a second circuit design having the specified respective delays along the respective logic paths by adding delay elements to the initial circuit design based on the specified respective delays.

    Randomized logic against side channel attacks
    2.
    发明授权
    Randomized logic against side channel attacks 有权

    公开(公告)号：US10951391B2

    公开(公告)日：2021-03-16

    申请号：US15757658

    申请日：2016-09-06

    Applicant: Bar-Ilan University

    Inventor： Moshe Avital ,  Itamar Levy ,  Osnat Keren ,  Alexander Fish

    IPC: G06F11/30 ,  G06F12/14 ,  H04L9/00 ,  G06F21/72 ,  G09C1/00 ,  G06F21/75

    Abstract: A randomization element includes a logic input for inputting a logic signal, a logic output for outputting the input logic signal at a delay and a randomization element. The randomization elements introduces the delay between said logic input and said logic output and operates selectably in static mode and in dynamic mode in accordance with a mode control signal. A logic circuit may be formed with randomization elements interspersed amongst the logic gates, to obtain protection against side channel attacks by inputting a selected control sequence into the randomization elements.

    Secured memory
    3.
    发明授权
    Secured memory 有权

    公开(公告)号：US11586778B2

    公开(公告)日：2023-02-21

    申请号：US16769664

    申请日：2018-12-06

    Applicant: Bar-Ilan University

    Inventor： Robert Giterman ,  Itamar Levi ,  Yoav Weizman ,  Osnat Keren ,  Alexander Fish ,  Maoz Vizentovski

    IPC: G06F21/75 ,  G06F13/16 ,  G06F21/72 ,  G11C7/24

    Abstract: A hardware memory includes at least one memory cell, peripheral circuitry and randomization circuitry. The memory cell(s) store data, which may be written to, read from and held in the hardware memory. The peripheral circuitry reads and writes data to the memory cell(s) and may perform other functions necessary for facilitating the data read, write and hold. The randomization circuitry randomizes operations performed by the peripheral circuitry to reduce a correlation between the data and the current consumed by the hardware memory.

    Information redistribution to reduce side channel leakage
    4.
    发明授权
    Information redistribution to reduce side channel leakage 有权

    公开(公告)号：US11321460B2

    公开(公告)日：2022-05-03

    申请号：US17002807

    申请日：2019-02-28

    Applicant: Bar-Ilan University

    Inventor： Alexander Fish ,  Osnat Keren ,  Yoav Weizman ,  Matan Elkoni

    IPC: G06F21/55 ,  G06F21/75 ,  H03K19/0948 ,  H04L9/00 ,  H03K3/84 ,  H03K17/687

    Abstract: A logic circuit includes a data signal input, a computational module, a direct timing modulator and an amplitude and non-direct timing modulator. The data signal input inputs data signals. The computational module includes multiple logic elements interconnected to perform a logic function. The direct timing modulator modulates a propagation time of the input data signals from the data signal input to the computational unit, in accordance with a first set of control signals. The amplitude and non-direct timing modulator modulates the processing time of data signals by the computational module and the amplitude of data signals propagating through the computational module, in accordance with a second set of control signals.

    Multi-topology logic gates
    5.
    发明授权
    Multi-topology logic gates 有权

    公开(公告)号：US10169617B2

    公开(公告)日：2019-01-01

    申请号：US15301409

    申请日：2015-04-29

    Applicant: Bar-Ilan University

    Inventor： Alexander Fish ,  Moshe Avital ,  Hadar Dagan ,  Osnat Keren

    IPC: G06F11/00 ,  G06F21/75 ,  H03K19/177 ,  G06F21/76

    Abstract: An RMTL gate includes at least two logic blocks, where at least one of the logic blocks operates in multiple modes. The respective logic block mode(s) are selected by a topology selector which applies mode control signals to the logic blocks in order to obtain a selected topology for logic circuit operation. RMTL logic gates may be cascaded and/or interconnected to form an RMTL logic circuit with multiple logic gates which may operate with dynamically varying topologies. Use of random, semi-random or specified control sequences may protect the logic circuit against security attacks.

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