公开(公告)号：US06887752B2

公开(公告)日：2005-05-03

申请号：US10690316

申请日：2003-10-21

Applicant: Sota Shinohara ,  Koichi Takemura ,  Yasuhiro Tsujita ,  Hidemitsu Mori

Inventor： Sota Shinohara ,  Koichi Takemura ,  Yasuhiro Tsujita ,  Hidemitsu Mori

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

Abstract: In a semiconductor memory, a barrier layer formed of a first metal film, a metal nitride film and a second metal film laminated in the named order is formed under a lower electrode of a ferroelectric capacitor in a memory cell, in order to minimize a pealing and lifting of the lower electrode from an underlying plug in the process of forming a ferroelectric material film as a capacitor dielectric film and in its succeeding annealing process. The metal nitride film is formed of a nitride of a metal constituting the first or second metal film.

Abstract translation: 在半导体存储器中，在存储单元中的强电介质电容器的下部电极的下方形成由第一金属膜，金属氮化物膜和第二金属膜形成的阻挡层，以便将其剥离 并且在形成作为电容器电介质膜的铁电材料膜的过程中以及在其后续的退火工艺中，从下面的电极提升下电极。 金属氮化物膜由构成第一或第二金属膜的金属的氮化物形成。

公开(公告)号：US6162676A

公开(公告)日：2000-12-19

申请号：US144504

申请日：1998-08-31

Applicant: Hidemitsu Mori

Inventor： Hidemitsu Mori

IPC: H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L27/108 ,  H01L29/417

CPC classification number: H01L27/10852 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/41725 ,  H01L29/41775 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate, a first etching stopper insulating film, a first insulating interlayer, a pair of first contact holes, first buried conductive layers, a first interconnection formed on one of the first buried conductive layers, a second insulating interlayer, a second contact hole, a second buried conductive layer, and a second interconnection. The first contact holes are formed at a predetermined interval in a direction parallel to the surface of the semiconductor substrate so as to reach a semiconductor element formed on the semiconductor substrate through the first insulating interlayer and the etching stopper insulating film. The second contact hole is formed to reach the other first buried conductive layer through the second insulating interlayer corresponding to a portion above the first buried conductive layer. Each of the first contact holes is constituted by a small-diameter lower contact hole formed in the first etching stopper insulating film and a large-diameter upper contact hole formed in the first insulating interlayer, and the first buried conductive layers do not project from the surface of the first insulating interlayer.

Abstract translation: 本发明涉及一种半导体器件及其制造方法。 半导体器件包括半导体衬底，第一蚀刻停止绝缘膜，第一绝缘中间层，一对第一接触孔，第一掩埋导电层，形成在第一掩埋导电层之一上的第一互连，第二绝缘中间层， 第二接触孔，第二掩埋导电层和第二互连。 第一接触孔以与半导体衬底的表面平行的方向以预定的间隔形成，以便通过第一绝缘中间层和蚀刻停止绝缘膜到达形成在半导体衬底上的半导体元件。 第二接触孔形成为通过对应于第一掩埋导电层上方的部分的第二绝缘夹层到达另一个第一掩埋导电层。 每个第一接触孔由形成在第一蚀刻停止绝缘膜中的小直径下接触孔和形成在第一绝缘夹层中的大直径上接触孔构成，并且第一掩埋导电层不从 第一绝缘中间层的表面。

公开(公告)号：US06030894A

公开(公告)日：2000-02-29

申请号：US119541

申请日：1998-07-20

Applicant: Hiromitsu Hada ,  Toru Tatsumi ,  Naoki Kasai ,  Hidemitsu Mori

Inventor： Hiromitsu Hada ,  Toru Tatsumi ,  Naoki Kasai ,  Hidemitsu Mori

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/52 ,  H01L27/088 ,  H01L27/108 ,  H01L29/08 ,  H01L29/45 ,  H01L29/78 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/31

CPC classification number: H01L27/10888 ,  H01L21/28512 ,  H01L21/28525 ,  H01L21/28562 ,  H01L21/76879 ,  H01L23/485 ,  H01L29/0847 ,  H01L29/456 ,  H01L29/66477 ,  H01L29/66613 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10873 ,  H01L2924/0002

Abstract: On a main surface of a silicon substrate of one conductivity type, a diffusion layer of the opposite conductivity type is formed, and the main surface of the silicon substrate is covered by an insulator film. The insulator film is formed with a contact hole which extends to reach the diffusion layer of the opposite conductivity type. A contact plug is provided in the contact hole. The contact plug fills the contact hole and comprises a first silicon layer of the opposite conductivity type directly connected to the diffusion layer of the opposite conductivity type, a silicon-germanium alloy layer of the opposite conductivity type directly contact to the first silicon layer, and a second silicon layer of the opposite conductivity type directly contact to the silicon-germanium alloy layer. Wiring is provided on the surface of the insulator film in direct contact to the contact plug. As a result, increase in leakage at the junction of the diffusion layer is prevented by the low-resistance contact plug including the silicon-germanium alloy.

Abstract translation: 在一种导电类型的硅衬底的主表面上，形成相反导电型的扩散层，并且硅衬底的主表面被绝缘体膜覆盖。 绝缘膜形成有延伸到达相反导电类型的扩散层的接触孔。 在接触孔中设置接触塞。 接触塞填充接触孔，并且包括直接连接到相反导电类型的扩散层的相反导电类型的第一硅层，相反导电类型的硅 - 锗合金层直接接触第一硅层，以及 相反导电类型的第二硅层直接接触硅 - 锗合金层。 绝缘膜的表面设置有与接触插头直接接触的接线。 结果，通过包括硅 - 锗合金的低电阻接触塞来防止扩散层的接合处的泄漏增加。

公开(公告)号：US5808365A

公开(公告)日：1998-09-15

申请号：US781815

申请日：1997-01-09

Applicant: Hidemitsu Mori

Inventor： Hidemitsu Mori

IPC: H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/522 ,  H01L27/108 ,  H01L29/417 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L27/10852 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/5226 ,  H01L29/41725 ,  H01L29/41775 ,  H01L2924/0002

Abstract: The invention relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate, a first etching stopper insulating film, a first insulating interlayer, a pair of first contact holes, first buried conductive layers, a first interconnection formed on one of the first buried conductive layers, a second insulating interlayer, a second contact hole, a second buried conductive layer, and a second interconnection. The first contact holes are formed at a predetermined interval in a direction parallel to the surface of the semiconductor substrate so as to reach a semiconductor element formed on the semiconductor substrate through the first insulating interlayer and the etching stopper insulating film. The second contact hole is formed to reach the other first buried conductive layer through the second insulating interlayer corresponding to a portion above the first buried conductive layer. Each of the first contact holes is constituted by a small-diameter lower contact hole formed in the first etching stopper insulating film and a large-diameter upper cyontact hole formed in the first insulating interlayer, and the first buried conductive layers do not project from the surface of the first insulating interlayer.

Abstract translation: 本发明涉及一种半导体器件及其制造方法。 半导体器件包括半导体衬底，第一蚀刻停止绝缘膜，第一绝缘中间层，一对第一接触孔，第一掩埋导电层，形成在第一掩埋导电层之一上的第一互连，第二绝缘中间层， 第二接触孔，第二掩埋导电层和第二互连。 第一接触孔以与半导体衬底的表面平行的方向以预定的间隔形成，以便通过第一绝缘中间层和蚀刻停止绝缘膜到达形成在半导体衬底上的半导体元件。 第二接触孔形成为通过对应于第一掩埋导电层上方的部分的第二绝缘夹层到达另一个第一掩埋导电层。 每个第一接触孔由形成在第一蚀刻阻挡绝缘膜中的小直径下接触孔和形成在第一绝缘中间层中的大直径上电晕孔构成，并且第一掩埋导电层不从 第一绝缘中间层的表面。

公开(公告)号：US06534358B2

公开(公告)日：2003-03-18

申请号：US09838186

申请日：2001-04-20

Applicant: Takeshi Nakura ,  Hidemitsu Mori ,  Seiichi Takahashi

Inventor： Takeshi Nakura ,  Hidemitsu Mori ,  Seiichi Takahashi

IPC: H01L218242

CPC classification number: H01L28/55 ,  H01L21/3105 ,  H01L27/10855 ,  H01L27/10894

Abstract: An interlayer insulating film, contacts, and wirings are formed on a MOS transistor formed on a silicon substrate. Another interlayer insulating film and contacts are formed thereon. Subsequently, as a first heat treatment, a heat treatment is performed in a hydrogen atmosphere or a nitrogen- or otherwise-diluted hydrogen atmosphere at a temperature of the order of 300-500° C. for about 5-60 minutes, thereby recovering defects that occur in the MOS transistor and insulating film forming steps and the like. Then, a ferroelectric capacitor connected to either diffusion layer of the MOS transistor is formed along with wirings, electrodes, and the like. Thereafter, as a second heat treatment, a heat treatment is performed in nitrogen at a temperature of the order of 300-500° C. for about 5-60 minutes. This recovers defects that occur after the first heat treatment step.

Abstract translation: 在形成于硅衬底上的MOS晶体管上形成层间绝缘膜，触点和布线。 在其上形成另一层间绝缘膜和触点。 随后，作为第一热处理，在氢气氛或氮气或其它稀释的氢气氛中，在约300-500℃的温度下进行约5-60分钟的热处理，从而回收缺陷 发生在MOS晶体管和绝缘膜形成步骤等中。 然后，连接到MOS晶体管的任一扩散层的铁电电容器与布线，电极等一起形成。 此后，作为第二热处理，在氮气中在约300-500℃的温度下进行约5-60分钟的热处理。 这恢复了在第一热处理步骤之后发生的缺陷。

公开(公告)号：US6127231A

公开(公告)日：2000-10-03

申请号：US98526

申请日：1998-06-17

Applicant: Hidemitsu Mori

Inventor： Hidemitsu Mori

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L29/78

CPC classification number: H01L27/10888 ,  H01L21/823443 ,  H01L27/10894 ,  H01L27/10873

Abstract: A method of fabricating a semiconductor device using the steps of: (a) forming a large number of first transistors having a fixed gate electrode separation in a first region on a semiconductor substrate and forming a large number of second transistors having a gate electrode separation wider than that of the first transistors in a second region on the semiconductor substrate; (b) covering the entire surface of these first and second regions with an insulating film of fixed film thickness; and (c) forming a buried layer consisting of the insulating film between the gate electrodes of the first transistors by etching this entire insulating film and forming side walls consisting of the insulating film on electrodes of the second transistors. In step (c), the spaces between the gate electrodes of the first transistors are filled with insulating film in self-aligned fashion and side walls consisting of insulating film are formed on the gate electrodes of the second transistors so that the space between the gate electrodes, i.e. the diffusion layer of the first transistors, is covered with insulating film and is not exposed to the etching atmosphere.

Abstract translation: 一种使用以下步骤制造半导体器件的方法：（a）在半导体衬底上的第一区域中形成大量具有固定栅电极分离的第一晶体管，并形成大量具有栅电极分离宽度的第二晶体管 比半导体衬底上的第二区域中的第一晶体管的晶体管的厚度大; （b）用固定膜厚度的绝缘膜覆盖这些第一和第二区域的整个表面; 以及（c）通过蚀刻该整个绝缘膜，形成由第一晶体管的栅电极之间的绝缘膜构成的掩埋层，并在第二晶体管的电极上形成由绝缘膜构成的侧壁。 在步骤（c）中，第一晶体管的栅电极之间的空间以自对准的方式填充绝缘膜，并且在第二晶体管的栅电极上形成由绝缘膜构成的侧壁，使得栅极之间的空间 电极即第一晶体管的扩散层被绝缘膜覆盖，并且不暴露于蚀刻气氛。

公开(公告)号：US5946570A

公开(公告)日：1999-08-31

申请号：US974996

申请日：1997-11-20

Applicant: Naoki Kasai ,  Hiromitsu Hada ,  Hidemitsu Mori ,  Toru Tatsumi

Inventor： Naoki Kasai ,  Hiromitsu Hada ,  Hidemitsu Mori ,  Toru Tatsumi

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/04 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L2924/0002

Abstract: A memory cell of a semiconductor dynamic random access memory device requires a bit line contact hole open to a drain region of a cell transistor for connecting a bit line to the drain region and a node contact hole open to a source region for connecting a storage electrode of a stacked capacitor to the source region, and the bit line contact hole and the node contact hole are plugged with silicon layers; the silicon layers are epitaxially grown from the source and drain regions over an oxide-encapsulated gate electrode of the cell transistor so as to increase the contact areas; and the silicon layers are firstly anisotropically grown until reaching the upper surface of the oxide-encapsulated gate electrode, and, thereafter, isotropically grown so as to increase the contact areas.

Abstract translation: 半导体动态随机存取存储器件的存储单元需要对单元晶体管的漏极区域开放的位线接触孔，用于将位线连接到漏极区域，并且向源区域开放的节点接触孔用于连接存储电极 的堆叠电容器到源极区域，并且位线接触孔和节点接触孔被硅层堵塞; 硅层从单元晶体管的氧化物封装的栅电极上的源极和漏极区域外延生长，以增加接触面积; 首先各向异性生长硅层，直到达到氧化物封装的栅电极的上表面，然后各向同性地生长以增加接触面积。

公开(公告)号：US5895948A

公开(公告)日：1999-04-20

申请号：US936919

申请日：1997-09-25

Applicant: Hidemitsu Mori ,  Toru Tatsumi ,  Hiromitsu Hada ,  Naoki Kasai

Inventor： Hidemitsu Mori ,  Toru Tatsumi ,  Hiromitsu Hada ,  Naoki Kasai

IPC: H01L23/522 ,  H01L21/20 ,  H01L21/205 ,  H01L21/28 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L29/78 ,  H01L27/02 ,  H01L27/08

CPC classification number: H01L27/10852 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639 ,  H01L27/10888 ,  H01L27/10811 ,  H01L27/10873

Abstract: A silicon layer serving as a contact plug directly connected to a diffusion layer of a MOS transistor is provided. On a surface of an N.sup.- type diffusion layer in self-alignment with a silicon nitride layer spacer and a field oxide layer, an N.sup.+ type monocrystalline silicon layer formed by anisotropic selective epitaxial growth method is directly connected. The surface of the N.sup.+ type monocrystalline silicon layer is directly connected to an N.sup.+ type monocrystalline silicon layer formed by isotropic selective epitaxial growth.

Abstract translation: 提供用作直接连接到MOS晶体管的扩散层的接触插塞的硅层。 在与氮化硅层间隔物和场氧化物层自对准的N型扩散层的表面上，通过各向异性选择性外延生长法形成的N +型单晶硅层直接连接。 N +型单晶硅层的表面直接连接到通过各向同性选择性外延生长形成的N +型单晶硅层。

公开(公告)号：US08148774B2

公开(公告)日：2012-04-03

申请号：US12606634

申请日：2009-10-27

Applicant: Hidemitsu Mori ,  Kazuhiro Takimoto ,  Toshiyuki Shou ,  Kenji Sasaki ,  Yutaka Akiyama

Inventor： Hidemitsu Mori ,  Kazuhiro Takimoto ,  Toshiyuki Shou ,  Kenji Sasaki ,  Yutaka Akiyama

IPC: H01L29/66 ,  H01L21/8238

CPC classification number: H01L21/823892 ,  H01L21/26513 ,  H01L21/823493

Abstract: To provide a semiconductor device in which an interval between first wells can be shortened by improving a separation breakdown voltage between the first wells and a method for manufacturing the same. A semiconductor device includes a first conductivity type semiconductor substrate 1, second conductivity type first wells 2 and 3 disposed on a surface layer of the semiconductor substrate 1 with a predetermined interval between them, a first conductivity type second well 4 disposed between the first wells 2 and 3 on the surface layer of the semiconductor substrate 1 and having an impurity concentration higher than that of the semiconductor substrate, a first conductivity type third well 5 at least disposed below the second well 4 in the semiconductor substrate 1 and having an impurity concentration higher than that of the semiconductor substrate 1 and lower than that of the second well 4, and a first conductivity type fourth well 11 at least disposed below the third well 5 in the semiconductor substrate 1 and having an impurity concentration higher than that of the semiconductor substrate 1 and lower than that of the second well 4.

Abstract translation: 提供一种半导体器件，其中可以通过改善第一阱之间的分离击穿电压及其制造方法来缩短第一阱之间的间隔。 半导体器件包括第一导电类型半导体衬底1，设置在半导体衬底1的表面层上的第二导电类型的第一阱2和3之间的预定间隔，设置在第一阱2之间的第一导电类型第二阱4 并且在半导体衬底1的表面层上具有杂质浓度高于半导体衬底1的杂质浓度的第一导电类型第三阱5，至少设置在半导体衬底1中的第二阱4的下方并且杂质浓度更高 比半导体衬底1低，而低于第二阱4，以及第一导电类型的第四阱11，其至少设置在半导体衬底1中的第三阱5的下方，其杂质浓度高于半导体衬底的杂质浓度 1且低于第二孔4的厚度。

公开(公告)号：US06730955B2

公开(公告)日：2004-05-04

申请号：US10100336

申请日：2002-03-18

Applicant: Sota Shinohara ,  Koichi Takemura ,  Yasuhiro Tsujita ,  Hidemitsu Mori

Inventor： Sota Shinohara ,  Koichi Takemura ,  Yasuhiro Tsujita ,  Hidemitsu Mori

IPC: H01L2968

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

Abstract: In a semiconductor memory, a barrier layer formed of a first metal film, a metal nitride film and a second metal film laminated in the named order is formed under a lower electrode of a ferroelectric capacitor in a memory cell, in order to minimize a pealing and lifting of the lower electrode from an underlying plug in the process of forming a ferroelectric material film as a capacitor dielectric film and in its succeeding annealing process. The metal nitride film is formed of a nitride of a metal constituting the first or second metal film.