公开(公告)号：US06781188B2

公开(公告)日：2004-08-24

申请号：US10153738

申请日：2002-05-24

Applicant: Yasuo Nakatani

Inventor： Yasuo Nakatani

IPC: H01L2968

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: Disclosed is a nonvolatile semiconductor memory device in which a disturbance phenomenon can be prevented. A nonvolatile semiconductor memory device has a semiconductor substrate, and a floating gate electrode formed on the semiconductor substrate via a gate insulating film. The floating gate electrode includes a lower conductive layer formed on the gate insulating film and having a first width W1 in a channel width direction, and an upper conductive layer formed on the lower conductive layer and having a second width W2 wider than the first width W1 in the channel width direction.

Abstract translation: 公开了一种可以防止干扰现象的非易失性半导体存储器件。 非易失性半导体存储器件具有通过栅极绝缘膜形成在半导体衬底上的半导体衬底和浮栅电极。 浮栅电极包括形成在栅绝缘膜上并具有沟道宽度方向的第一宽度W1的下导电层和形成在下导电层上并具有比第一宽度W1宽的第二宽度W2的上导电层 在通道宽度方向上。

公开(公告)号：US06633082B1

公开(公告)日：2003-10-14

申请号：US09088048

申请日：1998-06-01

Applicant: Noriaki Oda ,  Akira Matsumoto

Inventor： Noriaki Oda ,  Akira Matsumoto

IPC: H01L2968

CPC classification number: H01L21/022 ,  H01L21/02129 ,  H01L21/02134 ,  H01L21/02282 ,  H01L21/31053 ,  H01L21/3124 ,  H01L21/3144 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76838 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  Y10S257/914 ,  H01L2924/00

Abstract: A semiconductor device is provided and contains a substrate, a first wiring layer, a first oxide film, a dielectric film, a first nitrogen layer, a second wiring layer, a via hole, and a second nitrogen layer. The first wiring layer is formed on the substrate, and the first oxide film formed on the first wiring layer. The dielectric film has a low dielectric constant and is disposed between the first and second wiring layers. The first nitrogen layer contains nitrogen and is formed in the first oxide film. The via hole is formed through the dielectric film and is disposed between the first wiring layer and the second wiring layer for electrically connecting the first wiring layer and the second wiring layer. The second nitrogen layer contains nitrogen and is formed on a side wall of the via hole. Since the first and second nitrogen layers prevent moisture from spreading to various portions of the semiconductor device, leak current between adjacent wirings of the wiring layers is prevented. Also, the chances that an opening will not form in the via hole when the via hole is created is reduced.

Abstract translation: 提供半导体器件，并且包含基板，第一布线层，第一氧化膜，电介质膜，第一氮层，第二布线层，通孔和第二氮层。 第一布线层形成在基板上，第一氧化膜形成在第一布线层上。 电介质膜具有低的介电常数并且设置在第一和第二布线层之间。 第一氮层含有氮并形成在第一氧化膜中。 通孔形成为通过电介质膜形成在第一布线层和第二布线层之间，用于电连接第一布线层和第二布线层。 第二氮层含有氮，形成在通孔的侧壁上。 由于第一和第二氮层防止水分扩散到半导体器件的各个部分，所以防止了布线层的相邻布线之间的漏电流。 此外，当通孔形成时，在通孔中不会形成开口的机会减少。

公开(公告)号：US06787816B1

公开(公告)日：2004-09-07

申请号：US09944522

申请日：2001-08-31

Applicant: Tatsing P. Chow ,  Jeffrey B. Fedison

Inventor： Tatsing P. Chow ,  Jeffrey B. Fedison

IPC: H01L2968

CPC classification number: H01L29/66363 ,  H01L29/1608 ,  H01L29/74

Abstract: A method is provided for forming one or more doped layers using ion-implantation in the fabrication of thyristor devices. For example, these thyristors may be made from single crystalline silicon carbide. According to one aspect of the invention, one of the required layers is formed by introducing dopants after crystal growth as opposed to conventional methods which involve doping during crystal growth. Specifically, impurities may be introduced by using the technique of ion implantation.

Abstract translation: 提供了一种用于在晶闸管器件的制造中使用离子注入形成一个或多个掺杂层的方法。 例如，这些晶闸管可以由单晶碳化硅制成。 根据本发明的一个方面，与晶体生长中涉及掺杂的常规方法相反，通过在晶体生长后引入掺杂剂来形成所需层之一。 具体地，可以通过使用离子注入技术引入杂质。

公开(公告)号：US06583458B1

公开(公告)日：2003-06-24

申请号：US09397502

申请日：1999-09-17

Applicant: Masao Hayashi ,  Taiji Ema ,  Narumi Ohkawa

Inventor： Masao Hayashi ,  Taiji Ema ,  Narumi Ohkawa

IPC: H01L2968

CPC classification number: H01L27/10894 ,  H01L27/1052 ,  H01L27/10852 ,  H01L28/90 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an interlayer insulation film formed on a substrate so as to cover first and second regions defined on the substrate, and a capacitor formed over the interlayer insulation film in the first region, wherein the interlayer insulation film includes, in the first region, a stepped part defined by a groove having a bottom surface lower in level than a surface of the interlayer insulation film in the second region.

Abstract translation: 半导体器件包括形成在基板上以覆盖限定在基板上的第一和第二区域的层间绝缘膜和形成在第一区域中的层间绝缘膜上的电容器，其中层间绝缘膜包括在第一区域 由第二区域中的具有比层间绝缘膜的表面低的底面的凹槽限定的阶梯部分。

公开(公告)号：US06730955B2

公开(公告)日：2004-05-04

申请号：US10100336

申请日：2002-03-18

Applicant: Sota Shinohara ,  Koichi Takemura ,  Yasuhiro Tsujita ,  Hidemitsu Mori

Inventor： Sota Shinohara ,  Koichi Takemura ,  Yasuhiro Tsujita ,  Hidemitsu Mori

IPC: H01L2968

CPC classification number: H01L27/11502 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/75

Abstract: In a semiconductor memory, a barrier layer formed of a first metal film, a metal nitride film and a second metal film laminated in the named order is formed under a lower electrode of a ferroelectric capacitor in a memory cell, in order to minimize a pealing and lifting of the lower electrode from an underlying plug in the process of forming a ferroelectric material film as a capacitor dielectric film and in its succeeding annealing process. The metal nitride film is formed of a nitride of a metal constituting the first or second metal film.

公开(公告)号：US06707078B1

公开(公告)日：2004-03-16

申请号：US10230729

申请日：2002-08-29

Applicant: Hidehiko Shiraiwa ,  Yider Wu ,  Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Darlene G. Hamilton

Inventor： Hidehiko Shiraiwa ,  Yider Wu ,  Jean Yee-Mei Yang ,  Mark T. Ramsbey ,  Darlene G. Hamilton

IPC: H01L2968

CPC classification number: H01L27/11568 ,  G11C16/0466 ,  H01L27/115

Abstract: One aspect of the present invention relates to a SONOS type non-volatile semiconductor memory device having improved erase speed, the device containing bitlines extending in a first direction; wordlines extending in a second direction, the wordlines comprising functioning wordlines and at least one dummy wordline, wherein the dummy wordline is positioned near at least one of a bitline contact and an edge of the core region, and the dummy wordline is treated so as not to cycle between on and off states. Another aspect of the present invention relates to a method of making a SONOS type non-volatile semiconductor memory device having improved erase speed, involving forming a plurality of bitlines extending in a first direction in the core region; forming a plurality of functioning wordlines extending in a second direction in the core region; forming at least one dummy wordline between the functioning wordlines and the periphery region or between the functioning wordlines and a bitline contact and treating the device so that the dummy wordline does not cycle between on and off states.

Abstract translation: 本发明的一个方面涉及一种具有改进的擦除速度的SONOS型非易失性半导体存储器件，该器件含有沿第一方向延伸的位线; 所述字线在第二方向上延伸，所述字线包括功能字线和至少一个伪字线，其中所述伪字线位于所述芯区域的位线接触和边缘中的至少一个附近，并且所述伪字线被处理为不 在开关状态之间循环。 本发明的另一方面涉及一种制造具有改进的擦除速度的SONOS型非易失性半导体存储器件的方法，包括形成在芯区域中沿第一方向延伸的多个位线; 形成在所述芯区域中沿第二方向延伸的多个功能字线; 在功能字线和外围区域之间或在功能字线和位线接触之间形成至少一个伪字线，并对器件进行处理，使得伪字线不会在导通和关断状态之间循环。

公开(公告)号：US06670661B2

公开(公告)日：2003-12-30

申请号：US10046123

申请日：2002-01-07

Applicant: Thomas Peter Haneder ,  Harald Bachhofer

Inventor： Thomas Peter Haneder ,  Harald Bachhofer

IPC: H01L2968

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L27/1203 ,  H01L29/78391

Abstract: A memory cell configuration includes, as a memory cell, a ferroelectric transistor having a first gate intermediate layer and a first gate electrode between source/drain regions at the surface of a semiconductor substrate. The first gate intermediate layer contains at least one ferroelectric layer. Beside the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are disposed between the source/drain regions, the second gate intermediate layer containing a dielectric layer. The first gate electrode and the second gate electrode are connected to one another through a diode structure. Strip-type doped well regions are provided in the semiconductor substrate, which well regions run between the source/drain regions of the respective ferroelectric transistor.

Abstract translation: 存储单元配置包括在半导体衬底的表面处的源/漏区之间具有第一栅中间层和第一栅电极的铁电晶体管作为存储单元。 第一栅极中间层包含至少一个铁电层。 在第一栅极中间层之外，第二栅极中间层和第二栅电极设置在源/漏区之间，第二栅极中间层包含电介质层。 第一栅电极和第二栅电极通过二极管结构彼此连接。 在半导体衬底中提供带状掺杂阱区，这些阱区在相应铁电晶体管的源极/漏极区之间延伸。

公开(公告)号：US06548841B2

公开(公告)日：2003-04-15

申请号：US10165024

申请日：2002-06-07

Applicant: Gary A. Frazier ,  Alan C. Seabaugh

Inventor： Gary A. Frazier ,  Alan C. Seabaugh

IPC: H01L2968

CPC classification number: G11C23/00 ,  H01H1/0094 ,  Y10S977/70 ,  Y10S977/708 ,  Y10S977/709

Abstract: A highly miniaturized nanomechanical transistor switch is fabricated using a mechanical cantilever which creates a conductive path between two electrodes in its deflected state. In one embodiment, the cantilever is deflected by an electrostatic attraction arising from a voltage potential between the cantilever and a control electrode. In another embodiment, the cantilever is formed of a material with high magnetic permeability, and is deflected in response to complementary magnetic fields induced in the cantilever and in an adjacent electrode. The nanomechanical switch can be fabricated using well known semiconductor fabrication techniques, although semiconductor materials are not necessary for fabrication. The switch can rely upon physical contact between the cantilever and the adjacent electrode for current flow, or can rely upon sufficient proximity between the cantilever and the adjacent electrode to allow for tunneling current flow.

公开(公告)号：US06544847B2

公开(公告)日：2003-04-08

申请号：US09915928

申请日：2001-07-26

Applicant: Chun-Lin Chen ,  Ting-S. Wang ,  Juinn-Sheng Chen

Inventor： Chun-Lin Chen ,  Ting-S. Wang ,  Juinn-Sheng Chen

IPC: H01L2968

CPC classification number: H01L27/11521 ,  G11C2216/10 ,  H01L27/11558

Abstract: The present invention discloses a method for fabricating a non-volatile memory structure from a single layer of polysilicon in a semiconductor substrate, wherein the semiconductor substrate with two active areas, first and second, are divided by isolation regions. In accordance with this method, a doped buried layer is formed in the first active area. Then, a first floating gate is formed on the buried layer and a second floating gate is formed on the second active area from the single layer of polysilicon. Next, two doped regions are formed at opposite sides of the second floating gate in the second active areas. Finally, a floating gate connection line is employed to connect the first and second floating gate for making sure that the two floating gates are in the same potential.

Abstract translation: 本发明公开了一种从半导体衬底中的单层多晶硅制造非易失性存储器结构的方法，其中具有第一和第二有效区域的半导体衬底被隔离区划分。 根据该方法，在第一有源区域中形成掺杂掩埋层。 然后，在掩埋层上形成第一浮栅，并且在第二有源区上形成第二浮栅，该第二浮栅是单层多晶硅。 接下来，在第二有源区域中的第二浮栅的相对侧形成两个掺杂区。 最后，采用浮栅连接线来连接第一和第二浮栅，以确保两个浮栅处于相同的电位。

公开(公告)号：US06417536B2

公开(公告)日：2002-07-09

申请号：US09111613

申请日：1998-07-07

Applicant: Wiebe B. De Boer ,  Marieke C. Martens

Inventor： Wiebe B. De Boer ,  Marieke C. Martens

IPC: H01L2968

CPC classification number: H01L28/84 ,  H01L27/1085 ,  H01L27/10852 ,  H01L28/82 ,  H01L29/94

Abstract: A semiconductor device with a semiconductor body (1) provided with a memory capacitor (12, 26) with a lower electrode (11, 23) consisting of a layer of semiconductor material (7, 23) having a rough surface (8, 24) formed by hemispherical grains (9, 25) of the relevant semiconductor material on which a dielectric layer (12, 27) and an upper electrode (13, 28) are provided. The semiconductor material from which the lower electrode is manufactured is Si1−xGex, wherein 0.2

Abstract translation: 一种具有半导体本体（1）的半导体器件，其具有由具有粗糙表面（8,24）的半导体材料层（7,23）组成的下电极（11,23）的存储电容器（12,26） 由相关半导体材料的半球形晶粒（9,25）形成，其上设置介电层（12,27）和上电极（13,28）。 制造下电极的半导体材料是Si1-xGex，其中0.2