公开(公告)号：US06710388B2

公开(公告)日：2004-03-23

申请号：US09801209

申请日：2001-03-07

Applicant: Thomas Peter Haneder ,  Hans Reisinger ,  Reinhard Stengl ,  Harald Bachhofer ,  Hermann Wendt ,  Wolfgang Hönlein

Inventor： Thomas Peter Haneder ,  Hans Reisinger ,  Reinhard Stengl ,  Harald Bachhofer ,  Hermann Wendt ,  Wolfgang Hönlein

IPC: H01L27108

CPC classification number: G11C11/22 ,  H01L29/78391

Abstract: A ferroelectric transistor suitable as a memory element has a first gate intermediate layer and a first gate electrode disposed on the surface of a semiconductor substrate and disposed between source/drain regions. The first gate intermediate layer contains at least one ferroelectric layer. In addition to the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are configured between the source/drain regions. The second gate intermediate layer contains a dielectric layer. The first gate electrode and the second gate electrode are connected to each other via a diode structure.

Abstract translation: 适合作为存储元件的铁电晶体管具有设置在半导体衬底的表面上并设置在源极/漏极区之间的第一栅极中间层和第一栅电极。 第一栅极中间层包含至少一个铁电层。 除了第一栅极中间层之外，在源极/漏极区域之间配置第二栅极中间层和第二栅极电极。 第二栅极中间层包含电介质层。 第一栅电极和第二栅极通过二极管结构彼此连接。

公开(公告)号：US06707082B2

公开(公告)日：2004-03-16

申请号：US10112272

申请日：2002-03-28

Applicant: Thomas Peter Haneder ,  Harald Bachhofer ,  Eugen Unger

Inventor： Thomas Peter Haneder ,  Harald Bachhofer ,  Eugen Unger

IPC: H01L2976

CPC classification number: H01L29/516 ,  H01L28/56

Abstract: In a ferroelectric transistor containing two source/drain zones with a channel region disposed there-between, a first dielectric intermediate layer containing Al2O3 is disposed on a surface of the channel region. A ferroelectric layer and a gate electrode are disposed above the first dielectric intermediate layer. The utilization of Al2O3 in the first dielectric intermediate layer results in the suppression of tunneling of compensation charges from the channel region into the first dielectric layer and thereby improves the time for data storage.

Abstract translation: 在其中设置有沟道区域的两个源极/漏极区域的铁电晶体管中，包含Al 2 O 3的第一电介质中间层设置在沟道区域的表面上。 铁电层和栅电极设置在第一电介质中间层的上方。 在第一介电中间层中利用Al 2 O 3导致补偿电荷从沟道区到第一介电层的隧穿，从而改善了数据存储的时间。

公开(公告)号：US06670661B2

公开(公告)日：2003-12-30

申请号：US10046123

申请日：2002-01-07

Applicant: Thomas Peter Haneder ,  Harald Bachhofer

Inventor： Thomas Peter Haneder ,  Harald Bachhofer

IPC: H01L2968

CPC classification number: H01L27/11502 ,  G11C11/22 ,  H01L27/1203 ,  H01L29/78391

Abstract: A memory cell configuration includes, as a memory cell, a ferroelectric transistor having a first gate intermediate layer and a first gate electrode between source/drain regions at the surface of a semiconductor substrate. The first gate intermediate layer contains at least one ferroelectric layer. Beside the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are disposed between the source/drain regions, the second gate intermediate layer containing a dielectric layer. The first gate electrode and the second gate electrode are connected to one another through a diode structure. Strip-type doped well regions are provided in the semiconductor substrate, which well regions run between the source/drain regions of the respective ferroelectric transistor.

Abstract translation: 存储单元配置包括在半导体衬底的表面处的源/漏区之间具有第一栅中间层和第一栅电极的铁电晶体管作为存储单元。 第一栅极中间层包含至少一个铁电层。 在第一栅极中间层之外，第二栅极中间层和第二栅电极设置在源/漏区之间，第二栅极中间层包含电介质层。 第一栅电极和第二栅电极通过二极管结构彼此连接。 在半导体衬底中提供带状掺杂阱区，这些阱区在相应铁电晶体管的源极/漏极区之间延伸。

公开(公告)号：US06548846B2

公开(公告)日：2003-04-15

申请号：US09734466

申请日：2000-12-11

Applicant: Hans Reisinger ,  Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Gerrit Lange ,  Harald Bachhofer ,  Martin Franosch ,  Herbert Schäfer

Inventor： Hans Reisinger ,  Volker Lehmann ,  Reinhard Stengl ,  Hermann Wendt ,  Gerrit Lange ,  Harald Bachhofer ,  Martin Franosch ,  Herbert Schäfer

IPC: H01L27108

CPC classification number: H01L27/1085 ,  H01L27/10805

Abstract: A storage capacitor for a DRAM has a dielectric composed of silicon nitride and has at least two electrodes disposed opposite one another across the dielectric. A material having a high tunneling barrier between the Fermi level of the material and the conduction band of the dielectric is used for the electrodes. Suitable materials for the electrodes are metals such as platinum, tungsten and iridium or silicides.

Abstract translation: 用于DRAM的存储电容器具有由氮化硅构成的电介质，并且在电介质上具有彼此相对设置的至少两个电极。 对于电极，使用在材料的费米能级和电介质的导带之间具有高隧道势垒的材料。 用于电极的合适材料是金属如铂，钨和铱或硅化物。

公开(公告)号：US06815224B2

公开(公告)日：2004-11-09

申请号：US10372983

申请日：2003-02-24

Applicant: Harald Bachhofer ,  Thomas Haneder ,  Oswald Spindler ,  Rainer Waser

Inventor： Harald Bachhofer ,  Thomas Haneder ,  Oswald Spindler ,  Rainer Waser

IPC: H01L2100

CPC classification number: H01L21/02197 ,  H01L21/02356 ,  H01L21/31691 ,  H01L28/55 ,  H01L28/56

Abstract: In a method for producing ferroelectric strontium bismuth tantalate having the composition SrxBiyTa2O9 (SBT) or SrxBiy(Ta, Nb)2O9 (SBTN), the element strontium, which is normally present in an amount y=2, is provided in excess in a range from 2.1≦y≦3.0. This makes it possible to carry out the heat treatment step for converting the deposited material into the ferroelectric phase at a temperature T1, which is lower than 700° C. In addition, the strontium content x can be reduced from a nominal value of 1 to 0.7.

公开(公告)号：US06894330B2

公开(公告)日：2005-05-17

申请号：US09783187

申请日：2001-02-14

Applicant: Harald Bachhofer ,  Georg Braun ,  Thomas Peter Haneder ,  Wolfgang Hönlein ,  Marc Ullmann

Inventor： Harald Bachhofer ,  Georg Braun ,  Thomas Peter Haneder ,  Wolfgang Hönlein ,  Marc Ullmann

IPC: G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC classification number: G11C11/22

Abstract: The state of a ferroelectric transistor in a memory cell is read or stored, and the threshold voltage of further ferroelectric transistors in further memory cells in the memory matrix is increased during the reading or storing, or is increased permanently. A memory configuration including ferroelectric memory cells is also provided.

Abstract translation: 读取或存储存储单元中的铁电晶体管的状态，并且在读取或存储期间在存储矩阵中的另外的存储单元中的另外的铁电晶体管的阈值电压增加或永久地增加。 还提供了包括铁电存储单元的存储器配置。

公开(公告)号：US06469887B2

公开(公告)日：2002-10-22

申请号：US10011133

申请日：2001-11-13

Applicant: Harald Bachhofer ,  Thomas Haneder ,  Reinhard Stengl ,  Wolfgang Hönlein ,  Hans Reisinger

Inventor： Harald Bachhofer ,  Thomas Haneder ,  Reinhard Stengl ,  Wolfgang Hönlein ,  Hans Reisinger

IPC: H01G406

CPC classification number: H01L27/1085 ,  H01L21/31604 ,  H01L28/40 ,  H01L28/56

Abstract: A capacitor for a semiconductor configuration and a method for producing a dielectric layer for the capacitor. The dielectric layer consists of cerium oxide, zirconium oxide, hafnium oxide or various films of the materials.

公开(公告)号：US06614066B2

公开(公告)日：2003-09-02

申请号：US10113418

申请日：2002-04-01

Applicant: Reinhard Stengl ,  Hans Reisinger ,  Thomas Haneder ,  Harald Bachhofer

Inventor： Reinhard Stengl ,  Hans Reisinger ,  Thomas Haneder ,  Harald Bachhofer

IPC: H01L2976

CPC classification number: H01L29/516 ,  H01L29/78391

Abstract: A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.

公开(公告)号：US06455328B2

公开(公告)日：2002-09-24

申请号：US09781675

申请日：2001-02-12

Applicant: Harald Bachhofer ,  Walter Hartner ,  Guenther Schindler ,  Thomas Peter Haneder ,  Wolfgang Hoenlein

Inventor： Harald Bachhofer ,  Walter Hartner ,  Guenther Schindler ,  Thomas Peter Haneder ,  Wolfgang Hoenlein

IPC: H01L2100

CPC classification number: H01L27/11502 ,  H01L21/02197 ,  H01L21/02266 ,  H01L21/31691 ,  H01L27/11507 ,  H01L28/56

Abstract: The crystallization temperature of a ferroelectric layer (3) (dielectric) for a storage capacitor can be lowered by applying a very thin (CeO2 layer (2) to a first platinum electrode layer (1) of the storage capacitor before the ferroelectric layer is deposited. The dielectric layer (3) deposited in amorphous state is then crystallized by a temperature treatment step at a temperature in the range between 590° C. and 620° C. A second electrode layer (4) is then applied to complete the storage capacitor.

Abstract translation: 在沉积铁电体层之前，通过向存储电容器的第一铂电极层（1）施加非常薄的（CeO 2层（2）），可以降低用于存储电容器的铁电体层（3）（电介质）的结晶温度 沉积在非晶态的电介质层（3）然后通过温度处理步骤在590℃和620℃之间的温度下结晶。然后施加第二电极层（4）以完成储存电容器 。