Invention Grant
- Patent Title: Semiconductor device and fabrication process thereof
- Patent Title (中): 半导体器件及其制造工艺
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Application No.: US936919Application Date: 1997-09-25
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Publication No.: US5895948APublication Date: 1999-04-20
- Inventor: Hidemitsu Mori , Toru Tatsumi , Hiromitsu Hada , Naoki Kasai
- Applicant: Hidemitsu Mori , Toru Tatsumi , Hiromitsu Hada , Naoki Kasai
- Applicant Address: JPX Tokyo
- Assignee: NEC Corporation
- Current Assignee: NEC Corporation
- Current Assignee Address: JPX Tokyo
- Priority: JPX8-256912 19960927
- Main IPC: H01L23/522
- IPC: H01L23/522 ; H01L21/20 ; H01L21/205 ; H01L21/28 ; H01L21/768 ; H01L21/8234 ; H01L21/8242 ; H01L27/088 ; H01L27/108 ; H01L29/78 ; H01L27/02 ; H01L27/08
Abstract:
A silicon layer serving as a contact plug directly connected to a diffusion layer of a MOS transistor is provided. On a surface of an N.sup.- type diffusion layer in self-alignment with a silicon nitride layer spacer and a field oxide layer, an N.sup.+ type monocrystalline silicon layer formed by anisotropic selective epitaxial growth method is directly connected. The surface of the N.sup.+ type monocrystalline silicon layer is directly connected to an N.sup.+ type monocrystalline silicon layer formed by isotropic selective epitaxial growth.
Public/Granted literature
- US4757025A Method of making gate turn off switch with anode short and buried base Public/Granted day:1988-07-12
Information query
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