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    Seven-transistor static random-access memory bitcell with reduced read disturbance
    83.
    发明授权
    Seven-transistor static random-access memory bitcell with reduced read disturbance 有权

    公开(公告)号：US10037795B2

    公开(公告)日：2018-07-31

    申请号：US14499149

    申请日：2014-09-27

    Applicant: QUALCOMM Incorporated

    Inventor： Seong-Ook Jung ,  Younghwi Yang ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

    IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

    CPC classification number: G11C11/419 ,  G11C11/412

    Abstract: Systems and methods relate to a seven transistor static random-access memory (7T SRAM) bit cell which includes a first inverter having a first pull-up transistor, a first pull-down transistor, and a first storage node, and a second inverter having a second pull-up transistor, a second pull-down transistor, and a second storage node. The second storage node is coupled to gates of the first pull-up transistor and the first pull-down transistor. A transmission gate is configured to selectively couple the first storage node to gates of the second pull-up transistor and the second pull-down transistor during a write operation, a standby mode, and a hold mode, and selectively decouple the first storage node from gates of the first pull-up transistor and a first pull-down transistor during a read operation. The 7T SRAM bit cell can be read or written through an access transistor coupled to the first storage node.

    Static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation
    88.
    发明授权
    Static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation 有权
    静态随机存取存储器（SRAM）阵列在多种操作模式下具有基本恒定的工作产量

    公开(公告)号：US09424909B1

    公开(公告)日：2016-08-23

    申请号：US14659937

    申请日：2015-03-17

    Applicant: QUALCOMM Incorporated

    Inventor： Niladri Narayan Mojumder ,  Ping Liu ,  Stanley Seungchul Song ,  Zhongze Wang ,  Choh Fei Yeap

    IPC: G11C11/00 ,  G11C11/417 ,  G06F17/50 ,  G11C11/412

    CPC classification number: G11C11/417 ,  G06F17/5068 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C29/021 ,  G11C29/025 ,  G11C29/028 ,  G11C29/54 ,  G11C2029/1202 ,  G11C2029/1204

    Abstract: Aspects disclosed include static random access memory (SRAM) arrays having substantially constant operational yields across multiple modes of operation. In one aspect, a method of designing SRAM arrays with multiple modes operation is provided. The method includes determining performance characteristics associated with each mode of operation. SRAM bit cells configured to operate in each mode of operation are provided to the SRAM array. SRAM bit cells are biased to operate in a mode of operation using dynamic adaptive assist techniques, wherein the SRAM bit cells achieve a substantially constant operational yield across the modes. The SRAM bit cells have a corresponding type, wherein the number of SRAM bit cell types in the method is less than the number of modes of operation. Thus, each SRAM array may achieve a particular mode of operation without requiring a separate SRAM bit cell type for each mode, thereby reducing costs.

    Abstract translation: 所公开的方面包括在多种操作模式下具有基本恒定的操作成品率的静态随机存取存储器（SRAM）阵列。 在一个方面，提供了一种设计具有多种模式操作的SRAM阵列的方法。 该方法包括确定与每个操作模式相关联的性能特征。 配置为在每个操作模式下操作的SRAM位单元被提供给SRAM阵列。 SRAM位单元被偏置以在使用动态自适应辅助技术的操作模式下操作，其中SRAM位单元在整个模式下实现基本上恒定的运行产量。 SRAM位单元具有相应的类型，其中方法中的SRAM位单元类型的数量小于操作模式的数量。 因此，每个SRAM阵列可以实现特定的操作模式，而不需要用于每个模式的单独的SRAM位单元类型，从而降低成本。

    STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS WITH WORDLINE LANDING PADS SPLIT ACROSS BOUNDARY EDGES OF THE SRAM BIT CELLS
    90.
    发明申请
    STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS WITH WORDLINE LANDING PADS SPLIT ACROSS BOUNDARY EDGES OF THE SRAM BIT CELLS 有权
    静态随机访问存储器（SRAM）位元件，具有垂直栅极分离器，位于SRAM位元件的边界边界

    公开(公告)号：US20160163714A1

    公开(公告)日：2016-06-09

    申请号：US14559258

    申请日：2014-12-03

    Applicant: QUALCOMM Incorporated

    Inventor： Niladri Narayan Mojumder ,  Stanley Seungchul Song ,  Zhongze Wang ,  Kern Rim ,  Choh Fei Yeap

    IPC: H01L27/11 ,  G11C11/412 ,  G11C5/06 ,  H01L23/528 ,  H01L21/768

    CPC classification number: H01L27/11 ,  G11C5/063 ,  G11C8/14 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418 ,  H01L21/768 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/1104 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Static random access memory (SRAM) bit cells with wordline landing pads split across boundary edges of the SRAM bit cells are disclosed. In one aspect, an SRAM bit cell is disclosed employing write wordline in second metal layer, first read wordline in third metal layer, and second read wordline in fourth metal layer. Employing wordlines in separate metal layers allows wordlines to have wider widths, which decrease wordline resistance, decrease access time, and increase performance of SRAM bit cell. To employ wordlines in separate metal layers, multiple tracks in first metal layer are employed. To couple read wordlines to the tracks to communicate with SRAM bit cell transistors, landing pads are disposed on corresponding tracks inside and outside of a boundary edge of the SRAM bit cell. Landing pads corresponding to the write wordline are placed on corresponding tracks within the boundary edge of the SRAM bit cell.

    Abstract translation: 公开了在SRAM位单元的边界边缘分割的具有字线着色焊盘的静态随机存取存储器（SRAM）位单元。 一方面，公开了在第二金属层中采用写入字线，第三金属层中的第一读取字线和第四金属层中的第二读取字线的SRAM位单元。 在单独的金属层中使用字线允许字线具有更宽的宽度，这降低了字线电阻，减少了访问时间，并且提高了SRAM位单元的性能。 为了在单独的金属层中采用字线，采用第一金属层中的多个轨道。 为了将读取字线耦合到轨道以与SRAM位单元晶体管通信，着陆焊盘设置在SRAM位单元的边界内部和外部的对应轨道上。 对应于写入字线的着陆焊盘被放置在SRAM位单元的边界边缘内的对应的轨道上。

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