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    MTP-Thyristor Memory Cell Circuits and Methods of Operation
    71.
    发明申请
    MTP-Thyristor Memory Cell Circuits and Methods of Operation 审中-公开
    MTP晶闸管存储单元电路和操作方法

    公开(公告)号：US20170018299A1

    公开(公告)日：2017-01-19

    申请号：US15283254

    申请日：2016-09-30

    Applicant: Kilopass Technology, Inc.

    Inventor： Colin Stewart Bill ,  Harry Luan

    IPC: G11C11/39

    CPC classification number: G11C11/39 ,  G11C5/06 ,  G11C5/063 ,  G11C16/0466 ,  G11C16/14 ,  H01L27/1027 ,  H01L29/7404 ,  H01L29/7436 ,  H01L29/792

    Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

    Abstract translation: 描述了用于集成电路存储器阵列的MTP（许多次可编程）存储器单元。 该单元包括MTP器件和互连的晶闸管，使得MTP器件在读取或验证操作期间触发晶闸管导通。 使用数据存储单元和参考存储单元之间的阈值电压的差来确定数据存储单元中的信息。 可以为不同的存储器阵列要求构建不同的存储器单元结构。

    MTP-thyristor memory cell circuits and methods of operation
    73.
    发明授权
    MTP-thyristor memory cell circuits and methods of operation 有权
    MTP晶闸管存储单元电路及操作方法

    公开(公告)号：US09484068B2

    公开(公告)日：2016-11-01

    申请号：US15045112

    申请日：2016-02-16

    Applicant: Kilopass Technology, Inc.

    Inventor： Colin Stewart Bill ,  Harry Luan

    IPC: G11C11/39 ,  G11C5/06 ,  G11C16/14

    CPC classification number: G11C11/39 ,  G11C5/06 ,  G11C5/063 ,  G11C16/0466 ,  G11C16/14 ,  H01L27/1027 ,  H01L29/7404 ,  H01L29/7436 ,  H01L29/792

    Abstract: An MTP (Many Times Programmable) memory cell for integrated circuit memory arrays is described. The cell includes an MTP device and a thyristor interconnected so that the MTP device triggers the thyristor to turn on during a Read or Verify operation. The difference in threshold voltages between a data memory cell and a reference memory cell is used to determine the information in the data memory cell. Different memory cell structures may be constructed for different memory array requirements.

    Abstract translation: 描述了用于集成电路存储器阵列的MTP（许多次可编程）存储器单元。 该单元包括MTP器件和互连的晶闸管，使得MTP器件在读取或验证操作期间触发晶闸管导通。 使用数据存储单元和参考存储单元之间的阈值电压的差来确定数据存储单元中的信息。 可以为不同的存储器阵列要求构建不同的存储器单元结构。

    Thyristor-type memory device
    75.
    发明授权
    Thyristor-type memory device 失效
    晶闸管型存储器件

    公开(公告)号：US06967358B2

    公开(公告)日：2005-11-22

    申请号：US10777453

    申请日：2004-02-12

    Applicant: Farid Nemati ,  James D. Plummer

    Inventor： Farid Nemati ,  James D. Plummer

    IPC: G11C11/41 ,  G11C11/39 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/11 ,  H01L29/417 ,  H01L29/423 ,  H01L29/74 ,  H01L29/87

    CPC classification number: H01L29/74 ,  G11C11/39 ,  H01L27/0617 ,  H01L27/0688 ,  H01L27/1023 ,  H01L27/1027 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/41716 ,  H01L29/42308 ,  H01L29/749 ,  H01L29/87

    Abstract: A thyristor device can be used to implement a variety of semiconductor memory circuits, including high-density memory-cell arrays and single cell circuits. In one example embodiment, the thyristor device includes doped regions of opposite polarity, and a first word line that is used to provide read and write access to the memory cell. A second word line is located adjacent to and separated by an insulative material from one of the doped regions of the thyristor device for write operations to the memory cell, for example, by enhancing the switching of the thyristor device from a high conductance state to a low conductance state and/or from the low conductance state to the high conductance. This type of memory circuit can be implemented to significantly reduce standby power consumption and access time.

    Abstract translation: 晶闸管器件可用于实现包括高密度存储单元阵列和单个单元电路的各种半导体存储器电路。 在一个示例性实施例中，晶闸管器件包括具有相反极性的掺杂区域，以及用于向存储器单元提供读取和写入访问的第一字线。 第二字线例如通过增强晶闸管器件从高电导状态到高电导状态的切换而位于与用于写入操作的晶闸管器件的掺杂区域中的一个的绝缘材料相邻并由绝缘材料隔开的位置 低电导状态和/或从低电导状态到高电导状态。 可以实现这种类型的存储器电路，以显着降低待机功耗和访问时间。

    Dynamic data restore in thyristor-based memory device
    76.
    发明授权
    Dynamic data restore in thyristor-based memory device 失效
    基于晶闸管的存储器件中的动态数据恢复

    公开(公告)号：US06885581B2

    公开(公告)日：2005-04-26

    申请号：US10472737

    申请日：2002-04-05

    Applicant: Farid Nemati ,  Hyun-Jin Cho ,  Robert Homan Igehy

    Inventor： Farid Nemati ,  Hyun-Jin Cho ,  Robert Homan Igehy

    IPC: G11C7/00 ,  G11C11/00 ,  G11C11/39 ,  H01L29/866

    CPC classification number: G11C11/39

    Abstract: A dynamically-operating restoration circuit (106) is used to apply a voltage or current restore pulse signal to thyristor-based memory cells (108) and therein restore data in the cell using the internal positive feedback loop of the thyristor (110). In one example implementation, the internal positive feedback loop in the thyristor (110) is used to restore the conducting state of a device after the thyristor current drops below the holding current. A pulse and/or periodic waveform are defined and applied to ensure that the thyristor is not released from its conducting state. The time average of the periodic restore current in the thyristor may be lower than the holding current threshold. While not necessarily limited to memory cells that are thyristor-based, various embodiments of the invention have been found to be the particularly useful for high-speed, low-power memory cells in which a thin capacitively-coupled thyristor is used to provide a bi-stable storage element.

    Abstract translation: 使用动态操作的恢复电路（106）将电压或电流恢复脉冲信号施加到基于晶闸管的存储器单元（108），并且其中使用晶闸管（110）的内部正反馈环路在单元中恢复数据。 在一个示例实现中，晶闸管（110）中的内部正反馈环路用于在晶闸管电流下降到保持电流之前恢复器件的导通状态。 定义并施加脉冲和/或周期波形以确保晶闸管不从其导通状态释放。 晶闸管周期性恢复电流的时间平均值可能低于保持电流阈值。 虽然不一定限于基于晶闸管的存储器单元，但是已经发现本发明的各种实施例对于其中使用薄电容耦合晶闸管来提供双向的高速，低功率存储器单元特别有用 稳定存储元件

    Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states
    78.
    发明申请
    Nonvolatile memory cell without a dielectric antifuse having high- and low-impedance states 有权
    不具有高阻抗状态和低阻抗状态的介质反熔丝的非易失性存储单元

    公开(公告)号：US20050052915A1

    公开(公告)日：2005-03-10

    申请号：US10955549

    申请日：2004-09-29

    Applicant: S. Herner ,  Andrew Walker

    Inventor： S. Herner ,  Andrew Walker

    IPC: G11C7/00 ,  G11C11/39 ,  G11C17/06 ,  G11C17/16 ,  G11C29/00 ,  H01L21/336 ,  H01L21/82 ,  H01L27/24 ,  H01L29/73 ,  H01L45/00

    CPC classification number: H01L45/1233 ,  G11C5/02 ,  G11C11/39 ,  G11C17/06 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/77 ,  H01L27/1021

    Abstract: A memory cell according to the present invention comprises a bottom conductor, a doped semiconductor pillar, and a top conductor. The memory cell does not include a dielectric rupture antifuse separating the doped semiconductor pillar from either conductor, or within the semiconductor pillar. The memory cell is formed in a high-impedance state, in which little or no current flows between the conductors on application of a read voltage. Application of a programming voltage programs the cell, converting the memory cell from its initial high-impedance state to a low-impedance state. A monolithic three dimensional memory array of such cells can be formed, comprising multiple memory levels, the levels monolithically formed above one another.

    Abstract translation: 根据本发明的存储器单元包括底部导体，掺杂半导体柱和顶部导体。 存储单元不包括将掺杂半导体柱与任一导体或半导体柱分离的介电破裂反熔丝。 存储单元形成为在施加读取电压时在导体之间很少或没有电流流过的高阻抗状态。 应用编程电压对单元进行编程，将存储单元从其初始高阻抗状态转换为低阻抗状态。 可以形成这样的单元的单片三维存储器阵列，其包括多个存储器级，彼此之间单独形成的电平。

    Memory cell having negative differential resistance devices
    79.
    发明授权
    Memory cell having negative differential resistance devices 有权
    具有负差分电阻器件的存储单元

    公开(公告)号：US5953249A

    公开(公告)日：1999-09-14

    申请号：US210077

    申请日：1998-12-11

    Applicant: Jan P. van der Wagt

    Inventor： Jan P. van der Wagt

    IPC: G11C5/14 ,  G11C11/39 ,  G11C11/56 ,  H01L29/205

    CPC classification number: B82Y10/00 ,  G11C11/39 ,  G11C11/56 ,  G11C5/142 ,  G11C2211/5614

    Abstract: A memory system is organized as a matrix including a memory cell at each intersection of a bit line with write and read word lines. Each memory cell comprises a first FET 20 having its gate coupled to a write word line and its drain coupled to a bit line, a second FET 22 having its source coupled to the bit line and its drain coupled to a read word line, and first and second negative resistnce devices 24,26 coupled in series between a supply voltage and a substrate voltage, the common point SN of the series-connected negative resistance devices being coupled to the source of the first FET and to the gate of the second FET. Preferably, the first FET 20 is a p-channel device, the second FET 22 is an n-channel device, and the first and second negative resistance devices 24,26 are RTDs. In a second embodiment, a memory system has a memory cell at each intersection of a bit line with a word line. The memory cell comprises an FET having its gate coupled to a word line and one of its drain and source electrodes coupled to a bit line, first and second negative resistance devices 44,46 coupled in series between a supply voltage and a substrate voltage, the common point SN of the series-connected negative resistance devices being coupled to the other of the drain and source electrodes, and a capacitance 48 coupled between the common point of the series-connected negative resistance devices.

    Abstract translation: 存储器系统被组织为包括在位线与写入和读取字线的每个交叉处的存储器单元的矩阵。 每个存储器单元包括第一FET 20，其栅极耦合到写入字线并且其漏极耦合到位线;第二FET 22，其源极耦合到位线，其漏极耦合到读取字线， 以及串联连接在电源电压和衬底电压之间的第二负电阻器件24,26，串联连接的负电阻器件的公共点SN耦合到第一FET的源极和第二FET的栅极。 优选地，第一FET 20是p沟道器件，第二FET 22是n沟道器件，第一和第二负电阻器件24,26是RTD。 在第二实施例中，存储器系统在位线与字线的每个交叉处具有存储单元。 存储单元包括其栅极耦合到字线并且其漏极和源极中的一个耦合到位线的FET，在电源电压和衬底电压之间串联耦合的第一和第二负电阻器件44,46， 串联连接的负电阻器件的公共点SN耦合到漏极和源极电极中的另一个，以及耦合在串联连接的负电阻器件的公共点之间的电容48。

    Ternary logic circuit using resonant-tunneling transistors
    80.
    发明授权
    Ternary logic circuit using resonant-tunneling transistors 失效
    使用谐振隧道晶体管的三元逻辑电路

    公开(公告)号：US4956681A

    公开(公告)日：1990-09-11

    申请号：US310463

    申请日：1989-02-15

    Applicant: Naoki Yokoyama ,  Masao Taguchi

    Inventor： Naoki Yokoyama ,  Masao Taguchi

    IPC: H03K19/082 ,  F16L55/00 ,  G11C11/34 ,  G11C11/39 ,  G11C11/56 ,  H01L21/331 ,  H01L29/205 ,  H01L29/73 ,  H01L29/737 ,  H03K3/29 ,  H03K3/36 ,  H03K19/02 ,  H03K19/14 ,  H03K19/20

    CPC classification number: B82Y10/00 ,  F16L55/00 ,  G11C11/39 ,  G11C11/56 ,  H03K3/29 ,  H03K3/36 ,  G11C2211/5614

    Abstract: A logic gate including a resonant-tunneling transistor and a resistor connected in series thereto. The resonant-tunneling transistor has a superlattice structure. The resonant-tunneling transistor may be a resonant-tunneling hot electron transistor or a resonant-tunneling bipolar transistor. The resonant-tunneling transistor conducts a current between a collector and an emitter. The current has one of at least three different current values in response to a base voltage of one of three different voltage values. The third current value is between the first and second current values, and a second voltage value is between the first and third voltage values. The logic gate outputs one of at least three states, a high state, a low state and a state approximately between the high and low states in response to a signal applied to the logic gate. The signal has an amplitude of one of the first to third voltage values. A logic circuit includes at least three connected resonant-tunneling transistors. The logic circuit maintains at least three states, a high state, a low state, and a state approximately between the high and low states in the respective three resonant-tunneling transistors in response to a pulse signal applied to a base of one of the resonant-tunneling transistors.

    Abstract translation: 包括谐振隧穿晶体管和串联连接的电阻器的逻辑门。 谐振隧穿晶体管具有超晶格结构。 谐振隧穿晶体管可以是谐振隧道式热电子晶体管或谐振隧穿双极晶体管。 谐振隧穿晶体管在集电极和发射极之间导通电流。 响应于三个不同电压值之一的基极电压，电流具有至少三个不同电流值中的一个。 第三电流值在第一和第二电流值之间，第二电压值在第一和第三电压值之间。 响应于施加到逻辑门的信号，逻辑门输出至少三个状态中的一个，高状态，低状态和大致在高和低状态之间的状态。 该信号具有第一至第三电压值之一的振幅。 一个逻辑电路包括至少三个连接的谐振隧道晶体管。 逻辑电路响应于施加到谐振隧道晶体管中的一个的基极的脉冲信号，在三个谐振隧穿晶体管中保持至少三个状态，高状态，低状态和大致在高和低态之间的状态 隧道晶体管。

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