公开(公告)号：US20190149240A1

公开(公告)日：2019-05-16

申请号：US16150965

申请日：2018-10-03

Applicant: Massachusetts Institute of Technology

Inventor： Benjamin Roy Moss ,  Jason Scott Orcutt ,  Vladimir Marko Stojanovic

IPC: H04B10/516 ,  H01L31/18 ,  H01L31/105 ,  H01L21/8234 ,  G02F1/01 ,  G02F1/025

CPC classification number: H04B10/516 ,  G02F1/0121 ,  G02F1/0123 ,  G02F1/025 ,  G02F2203/15 ,  H01L21/823437 ,  H01L31/105 ,  H01L31/18

Abstract: Devices and techniques for integrated optical data communication. A method of encoding symbols in an optical signal may include encoding a first symbol by injecting charge carriers, at a first rate, into a semiconductor device, such as a PIN diode. The method may also include encoding a second symbol by injecting charge carriers, at a second rate, into the semiconductor device. The first rate may exceed the second rate. A modulator driver circuit may include a resistive circuit coupled between supply terminal and drive terminals. The modulator driver circuit may also include a control circuit coupled between a data terminal and the resistive circuit. The control circuit may modulate a resistance of the resistive circuit by selectively coupling one or more of a plurality of portions of the resistive circuit to the drive terminal based on data to be optically encoded. In some embodiments, a modulator driver circuit and an optical modulator may be integrated on the same die or stacked (3D integrated) die and connected with through-oxide or through-silicon vias.

公开(公告)号：US20190109134A1

公开(公告)日：2019-04-11

申请号：US16195162

申请日：2018-11-19

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hung-Li Chiang ,  Cheng-Yi Peng ,  Tsung-Yao Wen ,  Yee-Chia Yeo ,  Yen-Ming Chen

IPC: H01L27/092 ,  H01L21/8234 ,  H01L29/08 ,  H01L21/762 ,  H01L21/3105 ,  H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/31055 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A method of forming a semiconductor device includes etching a substrate to form two first trenches separated by a fin; filling the two first trenches with an isolation layer; and depositing a dielectric layer over the fin and the isolation layer. The method further includes forming a second trench in the dielectric layer over a channel region of the semiconductor device, the second trench exposing the isolation layer. The method further includes etching the isolation layer through the second trench to expose an upper portion of the fin in the channel region of the semiconductor device, and forming a dummy gate in the second trench over the isolation layer and engaging the upper portion of the fin.

公开(公告)号：US20180374859A1

公开(公告)日：2018-12-27

申请号：US16115711

申请日：2018-08-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Jine Park ,  Kee-Sang Kwon ,  Do-Hyoung Kim ,  Bo-Un Yoon ,  Keun-Hee Bai ,  Kwang-Yong Yang ,  Kyoung-Hwan Yeo ,  Yong-Ho Jeon

IPC: H01L27/11 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/762 ,  H01L29/78 ,  H01L27/092 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L27/1104 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1116 ,  H01L29/06 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848

Abstract: Semiconductor devices including a dummy gate structure on a fin are provided. A semiconductor device includes a fin protruding from a substrate. The semiconductor device includes a source/drain region in the fin, and a recess region of the fin that is between first and second portions of the source/drain region. Moreover, the semiconductor device includes a dummy gate structure overlapping the recess region, and a spacer that is on the fin and adjacent a sidewall of the dummy gate structure.

公开(公告)号：US20180358358A1

公开(公告)日：2018-12-13

申请号：US15801797

申请日：2017-11-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Kwan YU ,  Won Hyung KANG ,  Hyo Jin KIM ,  Sung Bu MIN

IPC: H01L27/088 ,  H01L27/02 ,  H01L29/04 ,  H01L29/06 ,  H01L29/36 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/08 ,  H01L29/165 ,  H01L21/762

CPC classification number: H01L27/0886 ,  H01L21/76224 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/36 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848 ,  H01L29/7853

Abstract: The semiconductor device includes a first fin-type pattern and a second fin-type pattern which extends along a first direction; a first gate structure and a second gate structure extending in a second direction, on the first fin-type pattern and the second fin-type pattern; and a shared epitaxial pattern which connects the first fin-type pattern and the second fin-type pattern between the first gate structure and the second gate structure. An upper surface of the shared epitaxial pattern includes a first shared slope and a second shared slope which connect the first gate structure and the second gate structure, a third shared slope which is in contact with the first gate structure and connects the first shared slope and the second shared slope, and a fourth shared slope which is in contact with the second gate structure and connects the first shared slope and the second shared slope.

公开(公告)号：US20180350695A1

公开(公告)日：2018-12-06

申请号：US15608159

申请日：2017-05-30

Applicant: International Business Machines Corporation

Inventor： Kangguo Cheng ,  Xin Miao ,  Wenyu Xu ,  Chen Zhang

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/10

CPC classification number: H01L21/823487 ,  H01L21/823437 ,  H01L29/1037 ,  H01L29/7827

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of fins on a substrate, wherein a hardmask is formed on each of the plurality of fins, forming a gate structure around the plurality of fins, selectively depositing a dummy dielectric on the hardmask on each of the plurality of fins, depositing a dielectric layer on the gate structure and around the dummy dielectrics, selectively removing the dummy dielectrics and the hardmasks with respect to the dielectric layer and the gate structure to create a plurality of openings exposing portions of the gate structure, and selectively removing the exposed portions of the gate structure through the plurality of the openings.

公开(公告)号：US20180341736A1

公开(公告)日：2018-11-29

申请号：US15949804

申请日：2018-04-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Yu-Jen CHEN ,  Ling-Sung WANG ,  I-Shan HUANG ,  Chan-yu HUNG

IPC: G06F17/50 ,  H01L27/088 ,  H01L27/02 ,  G03F1/70 ,  G03F1/36

CPC classification number: G06F17/5072 ,  G03F1/36 ,  G03F1/70 ,  G06F17/5068 ,  G06F17/5081 ,  H01L21/0274 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/1104

Abstract: A semiconductor structure includes: first and second active regions arranged in a first grid oriented in a first direction; and gate electrodes arranged spaced apart in a second grid and on corresponding ones of the active regions, the second grid being oriented in a second direction, the second direction being substantially perpendicular to the first direction; wherein: the first and second active regions are separated, relative to the second direction, by a gap; each gate electrode includes a first segment and a gate extension; each gate extension extends, relative to the second direction, beyond the corresponding active region and into the gap by a height HEXT, where HEXT≤(≈150 nm); and each gate extension, relative to a plane defined by the first and second directions, is substantially rectangular. In an embodiment, the height HEXT is HEXT≤(≈100 nm).

公开(公告)号：US20180337249A1

公开(公告)日：2018-11-22

申请号：US16048601

申请日：2018-07-30

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Fu-Jier FAN ,  Kong-Beng THEI ,  Szu-Hsien LIU

IPC: H01L29/66 ,  H01L29/49 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/311 ,  H01L21/285

CPC classification number: H01L29/6656 ,  H01L21/02271 ,  H01L21/28525 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823864 ,  H01L29/4916 ,  H01L29/6653 ,  H01L29/78

Abstract: A spacer structure and a fabrication method thereof are provided. First and second conductive structures are formed over a substrate. A first patterned dielectric layer is formed to cover the first conductive structure and exposing the second conductive structure. A second dielectric layer is formed to cover the first patterned dielectric layer and an upper surface and sidewalls of the second conductive structure. The second dielectric layer disposed over an upper surface of the first conductive structure and the upper surface of the second conductive structure is removed. The first patterned dielectric layer and the second dielectric layer disposed on sidewalls of the first conductive structure form a first spacer structure, and the second dielectric layer disposed on the sidewalls of the second conductive structure forms a second spacer structure. A width of the first spacer structure is larger than a width of the second spacer structure.

公开(公告)号：US20180337096A1

公开(公告)日：2018-11-22

申请号：US16048843

申请日：2018-07-30

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Alexander KALNITSKY ,  Kong-Beng THEI

IPC: H01L21/8234 ,  H01L27/088 ,  H01L21/311 ,  H01L21/02 ,  H01L21/033 ,  H01L21/8238

CPC classification number: H01L21/823468 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/0332 ,  H01L21/31144 ,  H01L21/823437 ,  H01L21/823864 ,  H01L27/088

Abstract: A spacer structure and a fabrication method thereof are provided. The method includes the following operations. First and second conductive structures are formed over a substrate. Dielectric layer is formed to cover the first and second conductive structures. Hard mask layer is formed over the dielectric layer. The hard mask layer covers the dielectric layer over the first conductive structure, and the hard mask layer has an opening exposing the dielectric layer over the second conductive structure. The dielectric layer exposed by the hard mask layer is etched to reduce thickness of the dielectric layer. The hard mask layer is removed. The dielectric layer is etched to form first main spacer on sidewall of the first conductive structure and second main spacer on sidewall of the second conductive structure. A first width of the first main spacer is greater than a second width of the second main spacer.

公开(公告)号：US20180331210A1

公开(公告)日：2018-11-15

申请号：US15912099

申请日：2018-03-05

Applicant: Renesas Electronics Corporation

Inventor： Kazuhisa MORI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L27/06 ,  H01L23/495 ,  H01L21/8234 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L21/823437 ,  H01L21/823456 ,  H01L23/4951 ,  H01L23/49562 ,  H01L23/49575 ,  H01L27/0629 ,  H01L27/0716 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/4238 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/49113 ,  H01L2924/00014

Abstract: A semiconductor device with a simplified structure including an energization control element and reverse coupling protection element, and a manufacturing method therefor. Its semiconductor substrate has deep and shallow trenches in its first surface. A first n-type impurity region lies in its second surface in contact with the deep trench bottom. A p-type impurity region includes: a p-type base region to make a pn junction with the first n-type region and in contact with the shallow trench bottom; and a back gate region joined to the p-type base region, lying in the first surface. A second n-type impurity region makes a pn junction with the p-type impurity region, lying in the first surface in contact with the shallow trench side face. An n+ source region makes a pn junction with the p-type region, lying in the first surface in contact with the side faces of deep and shallow trenches.

公开(公告)号：US20180323110A1

公开(公告)日：2018-11-08

申请号：US16038426

申请日：2018-07-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Huiming Bu ,  Andrew M. Greene ,  Balasubramanian Pranatharthiharan ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02 ,  H01L27/088 ,  H01L29/417 ,  H01L21/3213

CPC classification number: H01L21/823475 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/76802 ,  H01L21/76837 ,  H01L21/823418 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/41783 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795

Abstract: A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.