知搜-全球专利检索

  1. 登录
  2. 注册

搜索结果

2539 条记录 (耗时 0.052 秒)

    Metal-insulator-metal capacitors and methods of forming the same
    72.
    发明授权
    Metal-insulator-metal capacitors and methods of forming the same 有权

    公开(公告)号：US11848352B2

    公开(公告)日：2023-12-19

    申请号：US17467686

    申请日：2021-09-07

    申请人： Taiwan Semiconductor Manufacturing Company Limited

    发明人： Po-Chia Lai ,  Chun-Yen Lee ,  Stefan Rusu

    IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L49/02 ,  H01L27/08

    CPC分类号： H01L28/60 ,  H01L21/76838 ,  H01L23/5223 ,  H01L23/5226 ,  H01L27/0805

    摘要： Integrated circuit (IC) devices include a metal-insulator-metal (MIM) capacitor having a top electrode plate, a bottom electrode plate, and a plurality of intermediate electrode plates between the top electrode plate and the bottom electrode plate. A plurality of dielectric layers may separate each of the electrode plates of the MIM capacitor from adjacent plates of the MIM capacitor. Each of the intermediate electrode plates may have a thickness that is greater than a thickness of the top electrode plate and the bottom electrode plate. By providing multiple intermediate electrode plates between the top and bottom electrode plates of the MIM capacitor, and allocating the greatest plate thicknesses to the intermediate plates, the capacitance density may be increased in a given area of the IC device, which may provide increased performance for the IC device.

    Pre-charging bit lines through charge-sharing
    74.
    发明授权
    Pre-charging bit lines through charge-sharing 有权

    公开(公告)号：US11848047B2

    公开(公告)日：2023-12-19

    申请号：US17010901

    申请日：2020-09-03

    申请人： Taiwan Semiconductor Manufacturing Company Limited

    发明人： Mahmut Sinangil ,  Chiting Cheng ,  Hung-Jen Liao ,  Tsung-Yung Chang

    IPC分类号： G11C11/419 ,  G11C7/12

    CPC分类号： G11C11/419 ,  G11C7/12

    摘要： In one embodiment, a static random access memory (SRAM) device is provided. The SRAM device includes a memory cell, a bit line couple to the memory cell, a voltage supply line coupled to the memory cell, a control circuitry. The control circuitry is configured to charge a voltage supply line while the voltage supply line is electrically isolated from a bit line. A portion of the charge is transferred from the voltage supply line to the bit line. The voltage supply line is recharged while the voltage supply line is electrically isolated from the bit line storing the transferred portion of the charge. The memory cell is accessed using the recharge on the voltage supply line.

    MEMORY CHIPLET HAVING MULTIPLE ARRAYS OF MEMORY DEVICES AND METHODS OF FORMING THE SAME
    77.
    发明公开
    MEMORY CHIPLET HAVING MULTIPLE ARRAYS OF MEMORY DEVICES AND METHODS OF FORMING THE SAME 审中-公开

    公开(公告)号：US20230389341A1

    公开(公告)日：2023-11-30

    申请号：US18362192

    申请日：2023-07-31

    申请人： Taiwan Semiconductor Manufacturing Company Limited

    发明人： Chao-I WU ,  Yu-Ming LIN

    IPC分类号： H10B99/00

    CPC分类号： H10B99/00

    摘要： A disclosed memory structure includes a first memory region including a first memory array of SRAM memory devices, a second memory region including a second memory array of 1T1C memory devices, and a third memory region including a third memory array of FeFET memory devices. The memory structure further includes at least one data bus laterally extending across the first memory region, the second memory region, and third memory region and configured to provide data transfer among the first memory array, the second memory array, and the third memory array. The memory structure further includes a plurality of peripheral circuit devices formed at a semiconductor material layer of the memory structure, the peripheral circuit devices configured to control the first memory array, the second memory array, and the third memory array. At least one of the second memory array and the third memory array may be a 3-dimensional memory array.