公开(公告)号：US11442230B2

公开(公告)日：2022-09-13

申请号：US17097197

申请日：2020-11-13

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Yueh Ying Lee ,  Chien-Ying Wu ,  Sui-Ying Hsu ,  Chen-Hao Huang ,  Chien-Chang Lee ,  Chia-Ping Lai

IPC分类号： G02B6/34

摘要： An optical structure may be provided by forming a silicon grating structure over a dielectric material layer, depositing at least one dielectric material layer over the silicon grating structure, and depositing at least one dielectric etch stop layer over the at least one dielectric material layer. The at least one dielectric etch stop layer includes at least one dielectric material selected from silicon nitride and silicon oxynitride. A passivation dielectric layer may be formed over the at least one dielectric etch stop layer, and a patterned etch mask layer may be formed over the passivation dielectric layer. An opening may be formed through an unmasked portion of the passivation dielectric layer by performing an anisotropic etch process that etches the dielectric material selective to a silicon nitride or silicon oxynitride using the patterned etch mask layer as a masking structure. The at least one etch mask layer minimizes overetching.

公开(公告)号：US11532759B2

公开(公告)日：2022-12-20

申请号：US17159359

申请日：2021-01-27

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chen-Hao Huang ,  Hau-Yan Lu ,  Sui-Ying Hsu ,  Yuehying Lee ,  Chien-Ying Wu ,  Chia-Ping Lai

IPC分类号： H01L31/0203 ,  H01L31/0312 ,  H01L31/18 ,  H01L31/103 ,  H01L31/105 ,  H01L31/0352

摘要： At least one doped silicon region is formed in a silicon layer of a semiconductor substrate, and a silicon oxide layer is formed over the silicon layer. A germanium-containing material portion is formed in the semiconductor substrate to provide a p-n junction or a p-i-n junction including the germanium-containing material portion and one of the at least one doped silicon region. A capping material layer that is free of germanium is formed over the germanium-containing material portion. A first dielectric material layer is formed over the silicon oxide layer and the capping material layer. The first dielectric material layer includes a mesa region that is raised from the germanium-containing material portion by a thickness of the capping material layer. The capping material layer may be a silicon capping layer, or may be subsequently removed to form a cavity. Dark current is reduced for the germanium-containing material portion.

公开(公告)号：US20240201458A1

公开(公告)日：2024-06-20

申请号：US18589180

申请日：2024-02-27

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chen-Hao Huang ,  Sui-Ying Hsu ,  YuehYing Lee ,  Chia-Ping Lai ,  Chien-Ying Wu ,  Hau-Yan Lu

IPC分类号： G02B6/42 ,  G02B6/12 ,  G02B6/136 ,  G02B6/30 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L23/522 ,  H01L23/532 ,  H01L23/58

CPC分类号： G02B6/4248 ,  G02B6/12 ,  G02B6/12002 ,  G02B6/12004 ,  G02B6/136 ,  G02B6/4206 ,  G02B6/4274 ,  H01L23/53228 ,  G02B6/30 ,  G02B6/4228 ,  G02B6/4236 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L23/5226 ,  H01L23/585

摘要： An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.

公开(公告)号：US11848390B2

公开(公告)日：2023-12-19

申请号：US17853998

申请日：2022-06-30

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chen-Hao Huang ,  Hau-Yan Lu ,  Sui-Ying Hsu ,  YuehYing Lee ,  Chien-Ying Wu ,  Chia-Ping Lai

IPC分类号： H01L31/0203 ,  H01L31/0312 ,  H01L31/18 ,  H01L31/103 ,  H01L31/105 ,  H01L31/0352

CPC分类号： H01L31/0203 ,  H01L31/0312 ,  H01L31/035281 ,  H01L31/105 ,  H01L31/1037 ,  H01L31/1812

摘要： At least one doped silicon region is formed in a silicon layer of a semiconductor substrate, and a silicon oxide layer is formed over the silicon layer. A germanium-containing material portion is formed in the semiconductor substrate to provide a p-n junction or a p-i-n junction including the germanium-containing material portion and one of the at least one doped silicon region. A capping material layer that is free of germanium is formed over the germanium-containing material portion. A first dielectric material layer is formed over the silicon oxide layer and the capping material layer. The first dielectric material layer includes a mesa region that is raised from the germanium-containing material portion by a thickness of the capping material layer. The capping material layer may be a silicon capping layer, or may be subsequently removed to form a cavity. Dark current is reduced for the germanium-containing material portion.

公开(公告)号：US11940659B2

公开(公告)日：2024-03-26

申请号：US17460789

申请日：2021-08-30

申请人： Taiwan Semiconductor Manufacturing Company Limited

发明人： Chen-Hao Huang ,  Hau-Yan Lu ,  Sui-Ying Hsu ,  Yuehying Lee ,  Chien-Ying Wu ,  Chia-Ping Lai

IPC分类号： G02B6/12 ,  G02B6/136 ,  G02B6/30 ,  G02B6/42 ,  H01L23/532 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L23/522 ,  H01L23/58

CPC分类号： G02B6/4248 ,  G02B6/12 ,  G02B6/12002 ,  G02B6/12004 ,  G02B6/136 ,  G02B6/4206 ,  G02B6/4274 ,  H01L23/53228 ,  G02B6/30 ,  G02B6/4228 ,  G02B6/4236 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31116 ,  H01L23/5226 ,  H01L23/585

摘要： An optical integrated circuit (IC) structure includes: a substrate including a fiber slot formed in an upper surface of the substrate and extending from an edge of the substrate, and an undercut formed in the upper surface and extending from the fiber slot; a semiconductor layer disposed on the substrate; a dielectric structure disposed on the semiconductor layer; an interconnect structure disposed in the dielectric structure; a plurality of vents that extend through a coupling region of the dielectric structure and expose the undercut; a fiber cavity that extends through the coupling region of dielectric structure and exposes the fiber slot; and a barrier ring disposed in the dielectric structure, the barrier ring surrounding the interconnect structure and routed around the perimeter of the coupling region.